Lines Matching full:enable
23 #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
24 #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
25 #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
38 #define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
97 #define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
99 #define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
100 #define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
101 #define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
105 #define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
112 #define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
113 #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
114 #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
115 #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
116 #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
117 #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
118 #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
119 #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
120 #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
121 #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
122 #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
123 #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
124 #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
125 #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
126 #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
127 #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
128 #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
129 #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
136 #define CKEN io_p2v(0x41300004) /* Clock Enable Register */
154 #define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
155 #define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
156 #define CKEN_MEMC (22) /* Memory Controller Clock Enable */
158 #define CKEN_IM (20) /* Internal Memory Clock Enable */
159 #define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */
160 #define CKEN_USIM (18) /* USIM Unit Clock Enable */
161 #define CKEN_MSL (17) /* MSL Unit Clock Enable */
162 #define CKEN_LCD (16) /* LCD Unit Clock Enable */
163 #define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */
164 #define CKEN_I2C (14) /* I2C Unit Clock Enable */
165 #define CKEN_FICP (13) /* FICP Unit Clock Enable */
166 #define CKEN_MMC (12) /* MMC Unit Clock Enable */
167 #define CKEN_USB (11) /* USB Unit Clock Enable */
168 #define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */
169 #define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */
170 #define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */
171 #define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */
172 #define CKEN_I2S (8) /* I2S Unit Clock Enable */
173 #define CKEN_BTUART (7) /* BTUART Unit Clock Enable */
174 #define CKEN_FFUART (6) /* FFUART Unit Clock Enable */
175 #define CKEN_STUART (5) /* STUART Unit Clock Enable */
176 #define CKEN_HWUART (4) /* HWUART Unit Clock Enable */
177 #define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */
178 #define CKEN_SSP (3) /* SSP Unit Clock Enable */
179 #define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */
180 #define CKEN_AC97 (2) /* AC97 Unit Clock Enable */
181 #define CKEN_PWM1 (1) /* PWM1 Clock Enable */
182 #define CKEN_PWM0 (0) /* PWM0 Clock Enable */