Lines Matching full:enable
30 #define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
42 #define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */
44 #define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */
46 #define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */
48 #define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */
129 #define CKENA __REG(0x4134000C) /* A Clock Enable Register */
130 #define CKENB __REG(0x41340010) /* B Clock Enable Register */
131 #define CKENC __REG(0x41340024) /* C Clock Enable Register */
137 #define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */
157 * Clock Enable Bit
159 #define CKEN_LCD 1 /* < LCD Clock Enable */
160 #define CKEN_USBH 2 /* < USB host clock enable */
161 #define CKEN_CAMERA 3 /* < Camera interface clock enable */
162 #define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */
163 #define CKEN_USB2 6 /* < USB 2.0 client clock enable. */
164 #define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */
165 #define CKEN_SMC 9 /* < Static Memory Controller clock enable */
166 #define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */
167 #define CKEN_BOOT 11 /* < Boot rom clock enable */
168 #define CKEN_MMC1 12 /* < MMC1 Clock enable */
169 #define CKEN_MMC2 13 /* < MMC2 clock enable */
170 #define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */
171 #define CKEN_CIR 15 /* < Consumer IR Clock Enable */
172 #define CKEN_USIM0 17 /* < USIM[0] Clock Enable */
173 #define CKEN_USIM1 18 /* < USIM[1] Clock Enable */
174 #define CKEN_TPM 19 /* < TPM clock enable */
175 #define CKEN_UDC 20 /* < UDC clock enable */
176 #define CKEN_BTUART 21 /* < BTUART clock enable */
177 #define CKEN_FFUART 22 /* < FFUART clock enable */
178 #define CKEN_STUART 23 /* < STUART clock enable */
179 #define CKEN_AC97 24 /* < AC97 clock enable */
180 #define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */
181 #define CKEN_SSP1 26 /* < SSP1 clock enable */
182 #define CKEN_SSP2 27 /* < SSP2 clock enable */
183 #define CKEN_SSP3 28 /* < SSP3 clock enable */
184 #define CKEN_SSP4 29 /* < SSP4 clock enable */
185 #define CKEN_MSL0 30 /* < MSL0 clock enable */
186 #define CKEN_PWM0 32 /* < PWM[0] clock enable */
187 #define CKEN_PWM1 33 /* < PWM[1] clock enable */
188 #define CKEN_I2C 36 /* < I2C clock enable */
189 #define CKEN_INTC 38 /* < Interrupt controller clock enable */
190 #define CKEN_GPIO 39 /* < GPIO clock enable */
191 #define CKEN_1WIRE 40 /* < 1-wire clock enable */
192 #define CKEN_HSIO2 41 /* < HSIO2 clock enable */
196 #define CKEN_MMC3 5 /* < MMC3 Clock Enable */
197 #define CKEN_MVED 43 /* < MVED clock enable */
199 /* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
200 #define CKEN_PXA300_GCU 42 /* Graphics controller clock enable */
201 #define CKEN_PXA320_GCU 7 /* Graphics controller clock enable */