23 #define CI(c, p) { ci->c = PVR_##p(pvr); }  macro
34 	CI(ver_code, VERSION);  in set_cpuinfo_pvr_full()
65 	CI(pvr_user1, USER1);  in set_cpuinfo_pvr_full()
66 	CI(pvr_user2, USER2);  in set_cpuinfo_pvr_full()
68 	CI(mmu, USE_MMU);  in set_cpuinfo_pvr_full()
69 	CI(mmu_privins, MMU_PRIVINS);  in set_cpuinfo_pvr_full()
70 	CI(endian, ENDIAN);  in set_cpuinfo_pvr_full()
72 	CI(use_icache, USE_ICACHE);  in set_cpuinfo_pvr_full()
73 	CI(icache_tagbits, ICACHE_ADDR_TAG_BITS);  in set_cpuinfo_pvr_full()
74 	CI(icache_write, ICACHE_ALLOW_WR);  in set_cpuinfo_pvr_full()
76 	CI(icache_size, ICACHE_BYTE_SIZE);  in set_cpuinfo_pvr_full()
77 	CI(icache_base, ICACHE_BASEADDR);  in set_cpuinfo_pvr_full()
78 	CI(icache_high, ICACHE_HIGHADDR);  in set_cpuinfo_pvr_full()
80 	CI(use_dcache, USE_DCACHE);  in set_cpuinfo_pvr_full()
81 	CI(dcache_tagbits, DCACHE_ADDR_TAG_BITS);  in set_cpuinfo_pvr_full()
82 	CI(dcache_write, DCACHE_ALLOW_WR);  in set_cpuinfo_pvr_full()
84 	CI(dcache_size, DCACHE_BYTE_SIZE);  in set_cpuinfo_pvr_full()
85 	CI(dcache_base, DCACHE_BASEADDR);  in set_cpuinfo_pvr_full()
86 	CI(dcache_high, DCACHE_HIGHADDR);  in set_cpuinfo_pvr_full()
93 	CI(use_dopb, D_OPB);  in set_cpuinfo_pvr_full()
94 	CI(use_iopb, I_OPB);  in set_cpuinfo_pvr_full()
95 	CI(use_dlmb, D_LMB);  in set_cpuinfo_pvr_full()
96 	CI(use_ilmb, I_LMB);  in set_cpuinfo_pvr_full()
97 	CI(num_fsl, FSL_LINKS);  in set_cpuinfo_pvr_full()
99 	CI(irq_edge, INTERRUPT_IS_EDGE);  in set_cpuinfo_pvr_full()
100 	CI(irq_positive, EDGE_IS_POSITIVE);  in set_cpuinfo_pvr_full()
102 	CI(area_optimised, AREA_OPTIMISED);  in set_cpuinfo_pvr_full()
104 	CI(hw_debug, DEBUG_ENABLED);  in set_cpuinfo_pvr_full()
105 	CI(num_pc_brk, NUMBER_OF_PC_BRK);  in set_cpuinfo_pvr_full()
106 	CI(num_rd_brk, NUMBER_OF_RD_ADDR_BRK);  in set_cpuinfo_pvr_full()
107 	CI(num_wr_brk, NUMBER_OF_WR_ADDR_BRK);  in set_cpuinfo_pvr_full()
109 	CI(fpga_family_code, TARGET_FAMILY);  in set_cpuinfo_pvr_full()