88 	.rate	= 125000000,
92 	.rate	= 150000000,
182 		base_clock = cpu_clk.rate;  in tnetd7300_get_clock()
209 	int base_clock = bus_clk.rate;  in tnetd7300_set_clock()
213 		base_clock = bus_clk.rate;  in tnetd7300_set_clock()
222 		base_clock = cpu_clk.rate;  in tnetd7300_set_clock()
244 	bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,  in tnetd7300_init_clocks()
248 		cpu_clk.rate = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,  in tnetd7300_init_clocks()
251 		cpu_clk.rate = bus_clk.rate;  in tnetd7300_init_clocks()
253 	if (dsp_clk.rate == 250000000)  in tnetd7300_init_clocks()
255 			bootcr, dsp_clk.rate);  in tnetd7300_init_clocks()
340 		bus_clk.rate =  in tnetd7200_init_clocks()
344 			bus_clk.rate);  in tnetd7200_init_clocks()
349 		cpu_clk.rate =  in tnetd7200_init_clocks()
353 			cpu_clk.rate);  in tnetd7200_init_clocks()
362 			cpu_clk.rate = ((cpu_base / cpu_prediv) * cpu_mul)  in tnetd7200_init_clocks()
366 				cpu_clk.rate);  in tnetd7200_init_clocks()
371 			bus_clk.rate = cpu_clk.rate / 2;  in tnetd7200_init_clocks()
374 				dsp_mul * 2, bus_clk.rate);  in tnetd7200_init_clocks()
381 			bus_clk.rate = ((dsp_base / dsp_prediv) * dsp_mul)  in tnetd7200_init_clocks()
385 				dsp_mul * 2, bus_clk.rate);  in tnetd7200_init_clocks()
387 			cpu_clk.rate = bus_clk.rate;  in tnetd7200_init_clocks()
391 	usb_base = bus_clk.rate;  in tnetd7200_init_clocks()
398 	dsp_clk.rate = cpu_clk.rate;  in tnetd7200_init_clocks()
423 	return clk->rate;  in clk_get_rate()
457 		dsp_clk.rate = tnetd7300_dsp_clock();  in ar7_init_clocks()
464 	vbus_clk.rate = bus_clk.rate / 2;  in ar7_init_clocks()
468 long clk_round_rate(struct clk *clk, unsigned long rate)  in clk_round_rate()  argument
475 int clk_set_rate(struct clk *clk, unsigned long rate)  in clk_set_rate()  argument