27 static u32 irq_mask_addr[2];  variable
90 		val &= bcm_readl(irq_mask_addr[cpu] + src * sizeof(u32)); \
123 		if (!irq_mask_addr[cpu])				\
126 		val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
128 		bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\
145 		if (!irq_mask_addr[cpu])				\
148 		val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
153 		bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\
407 	irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);  in bcm63xx_init_irq()
409 	irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF);  in bcm63xx_init_irq()
414 		irq_mask_addr[0] += PERF_IRQMASK_3368_REG;  in bcm63xx_init_irq()
416 		irq_mask_addr[1] = 0;  in bcm63xx_init_irq()
423 		irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);  in bcm63xx_init_irq()
425 		irq_mask_addr[1] += PERF_IRQMASK_6328_REG(1);  in bcm63xx_init_irq()
435 		irq_mask_addr[0] += PERF_IRQMASK_6338_REG;  in bcm63xx_init_irq()
437 		irq_mask_addr[1] = 0;  in bcm63xx_init_irq()
444 		irq_mask_addr[0] += PERF_IRQMASK_6345_REG;  in bcm63xx_init_irq()
446 		irq_mask_addr[1] = 0;  in bcm63xx_init_irq()
453 		irq_mask_addr[0] += PERF_IRQMASK_6348_REG;  in bcm63xx_init_irq()
455 		irq_mask_addr[1] = 0;  in bcm63xx_init_irq()
462 		irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0);  in bcm63xx_init_irq()
464 		irq_mask_addr[1] += PERF_IRQMASK_6358_REG(1);  in bcm63xx_init_irq()
474 		irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0);  in bcm63xx_init_irq()
476 		irq_mask_addr[1] += PERF_IRQMASK_6362_REG(1);  in bcm63xx_init_irq()
486 		irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0);  in bcm63xx_init_irq()
488 		irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1);  in bcm63xx_init_irq()