Lines Matching full:59
226 #define PDC_CHASSIS_DT_NONE (0ULL << 59) /* data field unused */
228 #define PDC_CHASSIS_DT_PHYS_ADDR (1ULL << 59) /* physical address */
229 #define PDC_CHASSIS_DT_DATA_EXPECT (2ULL << 59) /* expected data */
230 #define PDC_CHASSIS_DT_ACTUAL (3ULL << 59) /* actual data */
231 #define PDC_CHASSIS_DT_PHYS_LOC (4ULL << 59) /* physical location */
232 #define PDC_CHASSIS_DT_PHYS_LOC_EXT (5ULL << 59) /* physical location extension */
233 #define PDC_CHASSIS_DT_TAG (6ULL << 59) /* tag */
234 #define PDC_CHASSIS_DT_SYNDROME (7ULL << 59) /* syndrome */
235 #define PDC_CHASSIS_DT_CODE_ADDR (8ULL << 59) /* code address */
236 #define PDC_CHASSIS_DT_ASCII_MSG (9ULL << 59) /* ascii message */
237 #define PDC_CHASSIS_DT_POST (10ULL << 59) /* POST code */
238 #define PDC_CHASSIS_DT_TIMESTAMP (11ULL << 59) /* timestamp */
239 #define PDC_CHASSIS_DT_DEV_STAT (12ULL << 59) /* device status */
240 #define PDC_CHASSIS_DT_DEV_TYPE (13ULL << 59) /* device type */
241 #define PDC_CHASSIS_DT_PB_DET (14ULL << 59) /* problem detail */
242 #define PDC_CHASSIS_DT_ACT_LEV (15ULL << 59) /* activity level/timeout */
243 #define PDC_CHASSIS_DT_SER_NUM (16ULL << 59) /* serial number */
244 #define PDC_CHASSIS_DT_REV_NUM (17ULL << 59) /* revision number */
245 #define PDC_CHASSIS_DT_INTERRUPT (18ULL << 59) /* interruption information */
246 #define PDC_CHASSIS_DT_TEST_NUM (19ULL << 59) /* test number */
247 #define PDC_CHASSIS_DT_STATE_CHG (20ULL << 59) /* major changes in system state */
248 #define PDC_CHASSIS_DT_PROC_DEALLOC (21ULL << 59) /* processor deallocate */
249 #define PDC_CHASSIS_DT_RESET (30ULL << 59) /* reset type and cause */
250 #define PDC_CHASSIS_DT_PA_LEGACY (31ULL << 59) /* legacy PA hex chassis code */