Lines Matching +full:inverted +full:- +full:rx
1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
12 #address-cells = <1>;
13 #size-cells = <1>;
16 dcr-parent = <&{/cpus/cpu@0}>;
24 #address-cells = <1>;
25 #size-cells = <0>;
31 clock-frequency = <300000000>; /* Filled in by U-Boot */
32 timebase-frequency = <300000000>; /* Filled in by U-Boot */
33 i-cache-line-size = <32>;
34 d-cache-line-size = <32>;
35 i-cache-size = <16384>; /* 16 kB */
36 d-cache-size = <16384>; /* 16 kB */
37 dcr-controller;
38 dcr-access-method = "native";
44 reg = <0x00000000 0x20000000>; /* Filled in by U-Boot */
47 UIC0: interrupt-controller {
49 interrupt-controller;
50 cell-index = <0>;
51 dcr-reg = <0x0c0 0x010>;
52 #address-cells = <0>;
53 #size-cells = <0>;
54 #interrupt-cells = <2>;
57 UIC1: interrupt-controller1 {
59 interrupt-controller;
60 cell-index = <1>;
61 dcr-reg = <0x0d0 0x010>;
62 #address-cells = <0>;
63 #size-cells = <0>;
64 #interrupt-cells = <2>;
66 interrupt-parent = <&UIC0>;
69 UIC2: interrupt-controller2 {
71 interrupt-controller;
72 cell-index = <2>;
73 dcr-reg = <0x0e0 0x010>;
74 #address-cells = <0>;
75 #size-cells = <0>;
76 #interrupt-cells = <2>;
78 interrupt-parent = <&UIC0>;
81 UIC3: interrupt-controller3 {
83 interrupt-controller;
84 cell-index = <3>;
85 dcr-reg = <0x0f0 0x010>;
86 #address-cells = <0>;
87 #size-cells = <0>;
88 #interrupt-cells = <2>;
90 interrupt-parent = <&UIC0>;
95 #address-cells = <1>;
96 #size-cells = <1>;
98 clock-frequency = <0>; /* Filled in by U-Boot */
100 SDRAM0: memory-controller {
101 compatible = "ibm,sdram-apm8018x";
102 dcr-reg = <0x010 0x002>;
107 dcr-reg = <0x180 0x062>;
108 num-tx-chans = <2>;
109 num-rx-chans = <16>;
110 #address-cells = <0>;
111 #size-cells = <0>;
112 interrupt-parent = <&UIC1>;
122 #address-cells = <1>;
123 #size-cells = <1>;
128 dcr-reg = <0x100 0x020>;
129 clock-frequency = <300000000>; /* Filled in by U-Boot */
131 RGMII0: emac-rgmii@400a2000 {
134 has-mdio;
137 TAH0: emac-tah@400a3000 {
142 TAH1: emac-tah@400a4000 {
148 compatible = "ibm,emac4", "ibm-emac4sync";
149 interrupt-parent = <&EMAC0>;
151 #interrupt-cells = <1>;
152 #address-cells = <0>;
153 #size-cells = <0>;
154 interrupt-map = </*Status*/ 0x0 &UIC0 0x13 0x4>;
156 local-mac-address = [000000000000]; /* Filled in by U-Boot */
157 mal-device = <&MAL0>;
158 mal-tx-channel = <0x0>;
159 mal-rx-channel = <0x0>;
160 cell-index = <0>;
161 max-frame-size = <9000>;
162 rx-fifo-size = <4096>;
163 tx-fifo-size = <2048>;
164 phy-mode = "rgmii";
165 phy-address = <0x2>;
167 phy-map = <0x00000000>;
168 rgmii-device = <&RGMII0>;
169 rgmii-channel = <0>;
170 tah-device = <&TAH0>;
171 tah-channel = <0>;
172 has-inverted-stacr-oc;
173 has-new-stacr-staopc;
177 compatible = "ibm,emac4", "ibm-emac4sync";
179 interrupt-parent = <&EMAC1>;
181 #interrupt-cells = <1>;
182 #address-cells = <0>;
183 #size-cells = <0>;
184 interrupt-map = </*Status*/ 0x0 &UIC0 0x14 0x4>;
186 local-mac-address = [000000000000]; /* Filled in by U-Boot */
187 mal-device = <&MAL0>;
188 mal-tx-channel = <1>;
189 mal-rx-channel = <8>;
190 cell-index = <1>;
191 max-frame-size = <9000>;
192 rx-fifo-size = <4096>;
193 tx-fifo-size = <2048>;
194 phy-mode = "rgmii";
195 phy-address = <0x3>;
197 phy-map = <0x00000000>;
198 rgmii-device = <&RGMII0>;
199 rgmii-channel = <1>;
200 tah-device = <&TAH1>;
201 tah-channel = <0>;
202 has-inverted-stacr-oc;
203 has-new-stacr-staopc;
204 mdio-device = <&EMAC0>;
210 stdout-path = "/plb/opb/serial@50001000";