19 	u64 msr = vcpu->arch.shregs.msr;  in emulate_tx_failure()
21 	tfiar = vcpu->arch.regs.nip & ~0x3ull;  in emulate_tx_failure()
23 	if (MSR_TM_SUSPENDED(vcpu->arch.shregs.msr))  in emulate_tx_failure()
29 	vcpu->arch.tfiar = tfiar;  in emulate_tx_failure()
31 	vcpu->arch.texasr = (vcpu->arch.texasr & 0x3ffffff) | texasr;  in emulate_tx_failure()
37  * instruction image is in vcpu->arch.emul_inst.  If the guest was in
44 	u32 instr = vcpu->arch.emul_inst;  in kvmhv_p9_tm_emulation()
45 	u64 msr = vcpu->arch.shregs.msr;  in kvmhv_p9_tm_emulation()
63 		newmsr = vcpu->arch.shregs.srr1;  in kvmhv_p9_tm_emulation()
69 		vcpu->arch.shregs.msr = newmsr;  in kvmhv_p9_tm_emulation()
70 		vcpu->arch.cfar = vcpu->arch.regs.nip - 4;  in kvmhv_p9_tm_emulation()
71 		vcpu->arch.regs.nip = vcpu->arch.shregs.srr0;  in kvmhv_p9_tm_emulation()
75 		if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206)) {  in kvmhv_p9_tm_emulation()
81 		if (!(vcpu->arch.hfscr & HFSCR_EBB)) {  in kvmhv_p9_tm_emulation()
86 		if ((msr & MSR_PR) && !(vcpu->arch.fscr & FSCR_EBB)) {  in kvmhv_p9_tm_emulation()
88 			vcpu->arch.fscr = (vcpu->arch.fscr & ~(0xffull << 56)) |  in kvmhv_p9_tm_emulation()
93 		bescr = vcpu->arch.bescr;  in kvmhv_p9_tm_emulation()
100 		vcpu->arch.bescr = bescr;  in kvmhv_p9_tm_emulation()
102 		vcpu->arch.shregs.msr = msr;  in kvmhv_p9_tm_emulation()
103 		vcpu->arch.cfar = vcpu->arch.regs.nip - 4;  in kvmhv_p9_tm_emulation()
104 		vcpu->arch.regs.nip = vcpu->arch.ebbrr;  in kvmhv_p9_tm_emulation()
118 		vcpu->arch.shregs.msr = newmsr;  in kvmhv_p9_tm_emulation()
123 		/* check for PR=1 and arch 2.06 bit set in PCR */  in kvmhv_p9_tm_emulation()
124 		if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206)) {  in kvmhv_p9_tm_emulation()
130 		if (!(vcpu->arch.hfscr & HFSCR_TM)) {  in kvmhv_p9_tm_emulation()
137 			vcpu->arch.fscr = (vcpu->arch.fscr & ~(0xffull << 56)) |  in kvmhv_p9_tm_emulation()
144 		vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |  in kvmhv_p9_tm_emulation()
154 		vcpu->arch.shregs.msr = msr;  in kvmhv_p9_tm_emulation()
160 		if (!(vcpu->arch.hfscr & HFSCR_TM)) {  in kvmhv_p9_tm_emulation()
167 			vcpu->arch.fscr = (vcpu->arch.fscr & ~(0xffull << 56)) |  in kvmhv_p9_tm_emulation()
179 		if (!(vcpu->arch.orig_texasr & TEXASR_FS)) {  in kvmhv_p9_tm_emulation()
189 		vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |  in kvmhv_p9_tm_emulation()
191 		vcpu->arch.shregs.msr &= ~MSR_TS_MASK;  in kvmhv_p9_tm_emulation()
198 		if (!(vcpu->arch.hfscr & HFSCR_TM)) {  in kvmhv_p9_tm_emulation()
205 			vcpu->arch.fscr = (vcpu->arch.fscr & ~(0xffull << 56)) |  in kvmhv_p9_tm_emulation()
212 		if (MSR_TM_ACTIVE(msr) || !(vcpu->arch.texasr & TEXASR_FS)) {  in kvmhv_p9_tm_emulation()
220 		vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |  in kvmhv_p9_tm_emulation()
222 		vcpu->arch.shregs.msr = msr | MSR_TS_S;  in kvmhv_p9_tm_emulation()