Lines Matching refs:__be32
39 __be32 potar; /* 0x.0 - Outbound translation address register */
40 __be32 potear; /* 0x.4 - Outbound translation extended address register */
41 __be32 powbar; /* 0x.8 - Outbound window base address register */
43 __be32 powar; /* 0x.10 - Outbound window attributes register */
49 __be32 pitar; /* 0x.0 - Inbound translation address register */
51 __be32 piwbar; /* 0x.8 - Inbound window base address register */
52 __be32 piwbear; /* 0x.c - Inbound window base extended address register */
53 __be32 piwar; /* 0x.10 - Inbound window attributes register */
59 __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
60 __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
61 __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
62 __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
63 __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
64 __be32 pex_config; /* 0x.014 - PCIE CONFIG Register */
65 __be32 pex_int_status; /* 0x.018 - PCIE interrupt status */
67 __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
68 __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
69 __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
70 __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
72 __be32 block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */
73 __be32 block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */
90 __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
92 __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
94 __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
96 __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
98 __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
99 __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
100 __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
101 __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
103 __be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */
105 __be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/
109 __be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/