Lines Matching refs:tiv
118 #define load_xts_16way(iv, src, dst, x0, x1, x2, x3, x4, x5, x6, x7, tiv, \ argument
129 vinserti128 $1, tivx, t0, tiv; \
130 vpxor (0*32)(src), tiv, x0; \
131 vmovdqu tiv, (0*32)(dst); \
134 gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
135 vpxor (1*32)(src), tiv, x1; \
136 vmovdqu tiv, (1*32)(dst); \
138 gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
139 vpxor (2*32)(src), tiv, x2; \
140 vmovdqu tiv, (2*32)(dst); \
142 gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
143 vpxor (3*32)(src), tiv, x3; \
144 vmovdqu tiv, (3*32)(dst); \
146 gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
147 vpxor (4*32)(src), tiv, x4; \
148 vmovdqu tiv, (4*32)(dst); \
150 gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
151 vpxor (5*32)(src), tiv, x5; \
152 vmovdqu tiv, (5*32)(dst); \
154 gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
155 vpxor (6*32)(src), tiv, x6; \
156 vmovdqu tiv, (6*32)(dst); \
158 gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
159 vpxor (7*32)(src), tiv, x7; \
160 vmovdqu tiv, (7*32)(dst); \
162 vextracti128 $1, tiv, tivx; \