95 	readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */  in xgene_ahci_init_memram()
97 	if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) {  in xgene_ahci_init_memram()
163 		fbs = readl(port_mmio + PORT_FBS);  in xgene_ahci_restart_engine()
165 		fbs = readl(port_mmio + PORT_FBS);  in xgene_ahci_restart_engine()
203 		port_fbs = readl(port_mmio + PORT_FBS);  in xgene_ahci_qc_issue()
226 	return (readl(diagcsr + CFG_MEM_RAM_SHUTDOWN) == 0 &&  in xgene_ahci_is_memram_inited()
227 	        readl(diagcsr + BLOCK_MEM_RDY) == 0xFFFFFFFF);  in xgene_ahci_is_memram_inited()
274 	val = readl(mmio + PORTCFG);  in xgene_ahci_set_phy_cfg()
277 	readl(mmio + PORTCFG);  /* Force a barrier */  in xgene_ahci_set_phy_cfg()
280 	readl(mmio + PORTPHY1CFG); /* Force a barrier */  in xgene_ahci_set_phy_cfg()
282 	readl(mmio + PORTPHY2CFG); /* Force a barrier */  in xgene_ahci_set_phy_cfg()
284 	readl(mmio + PORTPHY3CFG); /* Force a barrier */  in xgene_ahci_set_phy_cfg()
286 	readl(mmio + PORTPHY4CFG); /* Force a barrier */  in xgene_ahci_set_phy_cfg()
288 	val = readl(mmio + PORTPHY5CFG);  in xgene_ahci_set_phy_cfg()
291 	readl(mmio + PORTPHY5CFG); /* Force a barrier */  in xgene_ahci_set_phy_cfg()
292 	val = readl(mmio + PORTAXICFG);  in xgene_ahci_set_phy_cfg()
296 	readl(mmio + PORTAXICFG); /* Force a barrier */  in xgene_ahci_set_phy_cfg()
298 	val = readl(mmio + PORTRANSCFG);  in xgene_ahci_set_phy_cfg()
373 			val = readl(port_mmio + PORT_SCR_ERR);  in xgene_ahci_do_hardreset()
384 	val = readl(port_mmio + PORT_SCR_ERR);  in xgene_ahci_do_hardreset()
405 	portcmd_saved = readl(port_mmio + PORT_CMD);  in xgene_ahci_hardreset()
406 	portclb_saved = readl(port_mmio + PORT_LST_ADDR);  in xgene_ahci_hardreset()
407 	portclbhi_saved = readl(port_mmio + PORT_LST_ADDR_HI);  in xgene_ahci_hardreset()
408 	portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR);  in xgene_ahci_hardreset()
409 	portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI);  in xgene_ahci_hardreset()
464 	port_fbs = readl(port_mmio + PORT_FBS);  in xgene_ahci_pmp_softreset()
508 	port_fbs_save = readl(port_mmio + PORT_FBS);  in xgene_ahci_softreset()
514 	port_fbs = readl(port_mmio + PORT_FBS);  in xgene_ahci_softreset()
569 	if (!readl(hpriv->mmio + HOST_IRQ_STAT)) {  in xgene_ahci_handle_broken_edge_irq()
575 			if (readl(port_mmio + PORT_IRQ_STAT))  in xgene_ahci_handle_broken_edge_irq()
597 	irq_stat = readl(mmio + HOST_IRQ_STAT);  in xgene_ahci_irq_intr()
668 	readl(hpriv->mmio + HOST_IRQ_STAT); /* Force a barrier */  in xgene_ahci_hw_init()
670 	val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */  in xgene_ahci_hw_init()
675 	readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */  in xgene_ahci_hw_init()
677 	readl(ctx->csr_axi + INT_SLV_TMOMASK);  in xgene_ahci_hw_init()
686 	val = readl(ctx->csr_core + BUSCTLREG);  in xgene_ahci_hw_init()
691 	val = readl(ctx->csr_core + IOFMSTRWAUX);  in xgene_ahci_hw_init()
695 	val = readl(ctx->csr_core + IOFMSTRWAUX);  in xgene_ahci_hw_init()
710 	val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);  in xgene_ahci_mux_select()
713 	val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);  in xgene_ahci_mux_select()