39 	void __iomem	*reg;  member
47 	u32 reg;  in clk_pll_prepare()  local
49 	reg = readl(hbclk->reg);  in clk_pll_prepare()
50 	reg &= ~HB_PLL_RESET;  in clk_pll_prepare()
51 	writel(reg, hbclk->reg);  in clk_pll_prepare()
53 	while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)  in clk_pll_prepare()
55 	while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)  in clk_pll_prepare()
64 	u32 reg;  in clk_pll_unprepare()  local
66 	reg = readl(hbclk->reg);  in clk_pll_unprepare()
67 	reg |= HB_PLL_RESET;  in clk_pll_unprepare()
68 	writel(reg, hbclk->reg);  in clk_pll_unprepare()
74 	u32 reg;  in clk_pll_enable()  local
76 	reg = readl(hbclk->reg);  in clk_pll_enable()
77 	reg |= HB_PLL_EXT_ENA;  in clk_pll_enable()
78 	writel(reg, hbclk->reg);  in clk_pll_enable()
86 	u32 reg;  in clk_pll_disable()  local
88 	reg = readl(hbclk->reg);  in clk_pll_disable()
89 	reg &= ~HB_PLL_EXT_ENA;  in clk_pll_disable()
90 	writel(reg, hbclk->reg);  in clk_pll_disable()
97 	unsigned long divf, divq, vco_freq, reg;  in clk_pll_recalc_rate()  local
99 	reg = readl(hbclk->reg);  in clk_pll_recalc_rate()
100 	if (reg & HB_PLL_EXT_BYPASS)  in clk_pll_recalc_rate()
103 	divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT;  in clk_pll_recalc_rate()
104 	divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT;  in clk_pll_recalc_rate()
150 	u32 reg;  in clk_pll_set_rate()  local
154 	reg = readl(hbclk->reg);  in clk_pll_set_rate()
155 	if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) {  in clk_pll_set_rate()
157 		reg |= HB_PLL_EXT_BYPASS;  in clk_pll_set_rate()
158 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);  in clk_pll_set_rate()
160 		writel(reg | HB_PLL_RESET, hbclk->reg);  in clk_pll_set_rate()
161 		reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK);  in clk_pll_set_rate()
162 		reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT);  in clk_pll_set_rate()
163 		writel(reg | HB_PLL_RESET, hbclk->reg);  in clk_pll_set_rate()
164 		writel(reg, hbclk->reg);  in clk_pll_set_rate()
166 		while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)  in clk_pll_set_rate()
168 		while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)  in clk_pll_set_rate()
170 		reg |= HB_PLL_EXT_ENA;  in clk_pll_set_rate()
171 		reg &= ~HB_PLL_EXT_BYPASS;  in clk_pll_set_rate()
173 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);  in clk_pll_set_rate()
174 		reg &= ~HB_PLL_DIVQ_MASK;  in clk_pll_set_rate()
175 		reg |= divq << HB_PLL_DIVQ_SHIFT;  in clk_pll_set_rate()
176 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);  in clk_pll_set_rate()
178 	writel(reg, hbclk->reg);  in clk_pll_set_rate()
197 	u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4;  in clk_cpu_periphclk_recalc_rate()
209 	u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT;  in clk_cpu_a9bclk_recalc_rate()
224 	div = readl(hbclk->reg) & 0x1f;  in clk_periclk_recalc_rate()
253 	writel(div >> 1, hbclk->reg);  in clk_periclk_set_rate()
265 	u32 reg;  in hb_clk_init()  local
273 	rc = of_property_read_u32(node, "reg", &reg);  in hb_clk_init()
283 	hb_clk->reg = of_iomap(srnp, 0);  in hb_clk_init()
285 	BUG_ON(!hb_clk->reg);  in hb_clk_init()
286 	hb_clk->reg += reg;  in hb_clk_init()