Lines Matching +full:0 +full:x108

24 #define CPG_FRQCRA	0x00
25 #define CPG_FRQCRB	0x04
26 #define CPG_SD0CKCR	0x74
27 #define CPG_SD1CKCR	0x78
28 #define CPG_SD2CKCR	0x7c
29 #define CPG_PLLECR	0xd0
30 #define CPG_PLL0CR	0xd8
31 #define CPG_PLL1CR	0x28
32 #define CPG_PLL2CR	0x2c
33 #define CPG_PLL3CR	0xdc
34 #define CPG_CKSCR	0xc0
35 #define CPG_DSI0PHYCR	0x6c
36 #define CPG_DSI1PHYCR	0x70
38 #define CLK_ENABLE_ON_INIT BIT(0)
52 	{ "m2", "pll1", CPG_FRQCRA,  0 },
55 	{ NULL, NULL, 0, 0 },
59 	{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
61 	{ 12, 7 }, { 0, 0 }
65 	/* ZSEL == 0 */
66 	{ 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1 }, { 4, 1 }, { 5, 1 },
71 	{ 22, 16 }, { 24, 24 }, { 27, 48 }, { 0, 0 }
92 		u32 enable_bit = name[3] - '0';  in sh73a0_cpg_register_clock()
96 		case 0:  in sh73a0_cpg_register_clock()
112 			mult = ((readl(enable_reg) >> 24) & 0x3f) + 1;  in sh73a0_cpg_register_clock()
119 		u32 phy_no = name[3] - '0';  in sh73a0_cpg_register_clock()
125 		if (!(mult & 0x8000))  in sh73a0_cpg_register_clock()
128 			mult = (mult & 0x3f) + 1;  in sh73a0_cpg_register_clock()
153 		return clk_register_fixed_factor(NULL, name, parent_name, 0,  in sh73a0_cpg_register_clock()
156 		return clk_register_divider_table(NULL, name, parent_name, 0,  in sh73a0_cpg_register_clock()
157 						  cpg->reg + reg, shift, width, 0,  in sh73a0_cpg_register_clock()
170 	if (num_clks < 0) {  in sh73a0_cpg_clocks_init()
189 	cpg->reg = of_iomap(np, 0);  in sh73a0_cpg_clocks_init()
194 	writel(0x108, cpg->reg + CPG_SD0CKCR);  in sh73a0_cpg_clocks_init()
195 	writel(0x108, cpg->reg + CPG_SD1CKCR);  in sh73a0_cpg_clocks_init()
196 	writel(0x108, cpg->reg + CPG_SD2CKCR);  in sh73a0_cpg_clocks_init()
198 	for (i = 0; i < num_clks; ++i) {  in sh73a0_cpg_clocks_init()