107 	unsigned int mult;  in cpg_z_clk_recalc_rate()  local
111 	mult = 32 - (val >> __ffs(zclk->mask));  in cpg_z_clk_recalc_rate()
113 	return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,  in cpg_z_clk_recalc_rate()
121 	unsigned int min_mult, max_mult, mult;  in cpg_z_clk_determine_rate()  local
130 	mult = div64_ul(req->rate * 32ULL, prate);  in cpg_z_clk_determine_rate()
131 	mult = clamp(mult, min_mult, max_mult);  in cpg_z_clk_determine_rate()
133 	req->rate = div_u64((u64)prate * mult, 32);  in cpg_z_clk_determine_rate()
141 	unsigned int mult;  in cpg_z_clk_set_rate()  local
144 	mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,  in cpg_z_clk_set_rate()
146 	mult = clamp(mult, 1U, 32U);  in cpg_z_clk_set_rate()
152 		       ((32 - mult) << __ffs(zclk->mask)) & zclk->mask);  in cpg_z_clk_set_rate()
500 	rpcd2->fixed.mult = 1;  in cpg_rpcd2_clk_register()
553 	unsigned int mult = 1;  in rcar_gen3_cpg_clk_register()  local
574 		mult = (((value >> 24) & 0x7f) + 1) * 2;  in rcar_gen3_cpg_clk_register()
576 			mult *= 2;  in rcar_gen3_cpg_clk_register()
580 		mult = cpg_pll_config->pll1_mult;  in rcar_gen3_cpg_clk_register()
592 		mult = (((value >> 24) & 0x7f) + 1) * 2;  in rcar_gen3_cpg_clk_register()
594 			mult *= 2;  in rcar_gen3_cpg_clk_register()
598 		mult = cpg_pll_config->pll3_mult;  in rcar_gen3_cpg_clk_register()
610 		mult = (((value >> 24) & 0x7f) + 1) * 2;  in rcar_gen3_cpg_clk_register()
612 			mult *= 2;  in rcar_gen3_cpg_clk_register()
663 		mult = 1;  in rcar_gen3_cpg_clk_register()
712 					 __clk_get_name(parent), 0, mult, div);  in rcar_gen3_cpg_clk_register()