Lines Matching +full:0 +full:x4f4
18 #define RST_DFLL_DVCO 0x2F4
19 #define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */
20 #define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */
21 #define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */
24 #define DVFS_DFLL_RESET_SHIFT 0
27 #define CPU_FINETRIM_1_FCPU_1 BIT(0) /* fcpu0 */
35 #define CPU_FINETRIM_R_FCPU_1_SHIFT 0 /* fcpu0 */
36 #define CPU_FINETRIM_R_FCPU_1_MASK (0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT)
38 #define CPU_FINETRIM_R_FCPU_2_MASK (0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT)
40 #define CPU_FINETRIM_R_FCPU_3_MASK (0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT)
42 #define CPU_FINETRIM_R_FCPU_4_MASK (0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT)
44 #define CPU_FINETRIM_R_FCPU_5_MASK (0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT)
46 #define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
50 #define PLLC_BASE 0x80
51 #define PLLC_MISC2 0x88
52 #define PLLC_MISC 0x8c
53 #define PLLC2_BASE 0x4e8
54 #define PLLC2_MISC 0x4ec
55 #define PLLC3_BASE 0x4fc
56 #define PLLC3_MISC 0x500
57 #define PLLM_BASE 0x90
58 #define PLLM_MISC 0x9c
59 #define PLLP_BASE 0xa0
60 #define PLLP_MISC 0xac
61 #define PLLX_BASE 0xe0
62 #define PLLX_MISC 0xe4
63 #define PLLX_MISC2 0x514
64 #define PLLX_MISC3 0x518
65 #define PLLD_BASE 0xd0
66 #define PLLD_MISC 0xdc
67 #define PLLD2_BASE 0x4b8
68 #define PLLD2_MISC 0x4bc
69 #define PLLE_BASE 0xe8
70 #define PLLE_MISC 0xec
71 #define PLLA_BASE 0xb0
72 #define PLLA_MISC 0xbc
73 #define PLLU_BASE 0xc0
74 #define PLLU_MISC 0xcc
75 #define PLLRE_BASE 0x4c4
76 #define PLLRE_MISC 0x4c8
93 #define PLLE_AUX 0x48c
94 #define PLLC_OUT 0x84
95 #define PLLM_OUT 0x94
97 #define OSC_CTRL 0x50
103 #define CCLKG_BURST_POLICY 0x368
105 #define CLK_SOURCE_CSITE 0x1d4
106 #define CLK_SOURCE_EMC 0x19c
109 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
110 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
113 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
118 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
119 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
140 .divm_shift = 0,
149 { .pdiv = 1, .hw_val = 0 },
164 { .pdiv = 0, .hw_val = 0 },
168 { 12000000, 624000000, 104, 1, 2, 0 },
169 { 12000000, 600000000, 100, 1, 2, 0 },
170 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
171 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
172 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
173 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
174 { 0, 0, 0, 0, 0, 0 },
202 .divm_shift = 0,
211 { .pdiv = 1, .hw_val = 0 },
216 { .pdiv = 0, .hw_val = 0 },
220 { 12000000, 600000000, 100, 1, 2, 0 },
221 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
222 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
223 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
224 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
225 { 0, 0, 0, 0, 0, 0 },
243 .ext_misc_reg[0] = 0x4f0,
244 .ext_misc_reg[1] = 0x4f4,
245 .ext_misc_reg[2] = 0x4f8,
265 .ext_misc_reg[0] = 0x504,
266 .ext_misc_reg[1] = 0x508,
267 .ext_misc_reg[2] = 0x50c,
273 .divm_shift = 0,
275 .override_divm_shift = 0,
285 { .pdiv = 1, .hw_val = 0 },
287 { .pdiv = 0, .hw_val = 0 },
291 { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
292 { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
293 { 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */
294 { 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */
295 { 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */
296 { 0, 0, 0, 0, 0, 0 },
322 .divm_shift = 0,
336 { 0, 0, 0, 0, 0, 0 },
365 { 0, 0, 0, 0, 0, 0 },
402 { 0, 0, 0, 0, 0, 0 },
443 { .pdiv = 2, .hw_val = 0 },
444 { .pdiv = 0, .hw_val = 0 },
448 .divm_shift = 0,
462 { 0, 0, 0, 0, 0, 0 },
486 { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
487 { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
488 { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */
489 { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */
490 { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */
491 { 0, 0, 0, 0, 0, 0 },
523 { 0, 0, 0, 0, 0, 0 },
527 { .pdiv = 1, .hw_val = 0 },
542 { .pdiv = 0, .hw_val = 0 }
546 .divm_shift = 0,
575 .divm_shift = 0,
604 [ 0] = 13000000,
627 { .val = 0, .div = 1 },
633 { .val = 0, .div = 0 },
878 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
895 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768); in tegra114_fixed_clk_init()
906 pmc, 0, &pll_c_params, NULL); in tegra114_pll_init()
911 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra114_pll_init()
914 clk_base + PLLC_OUT, 1, 0, in tegra114_pll_init()
915 CLK_SET_RATE_PARENT, 0, NULL); in tegra114_pll_init()
919 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
924 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
935 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra114_pll_init()
938 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra114_pll_init()
939 CLK_SET_RATE_PARENT, 0, NULL); in tegra114_pll_init()
947 clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0, in tegra114_pll_init()
954 22, 0, &pll_u_lock); in tegra114_pll_init()
973 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
983 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
994 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq); in tegra114_pll_init()
997 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, in tegra114_pll_init()
998 clk_base + PLLRE_BASE, 16, 4, 0, in tegra114_pll_init()
1004 clk_base, 0, &pll_e_params, NULL); in tegra114_pll_init()
1008 #define CLK_SOURCE_VI_SENSOR 0x1a8
1022 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, in tegra114_periph_clk_init()
1030 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); in tegra114_periph_clk_init()
1037 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); in tegra114_periph_clk_init()
1040 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base, in tegra114_periph_clk_init()
1041 0, 48, periph_clk_enb_refcnt); in tegra114_periph_clk_init()
1044 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base, in tegra114_periph_clk_init()
1045 0, 82, periph_clk_enb_refcnt); in tegra114_periph_clk_init()
1053 29, 3, 0, &emc_lock); in tegra114_periph_clk_init()
1059 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base, in tegra114_periph_clk_init()
1064 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { in tegra114_periph_clk_init()
1135 { TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0 },
1136 { TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 },
1137 { TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 },
1138 { TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 },
1139 { TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 0 },
1140 { TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 0 },
1141 { TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1142 { TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1143 { TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1144 { TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1145 { TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1146 { TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0 },
1149 { TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0 },
1150 { TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0 },
1151 { TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
1152 { TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
1153 { TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0 },
1154 { TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0 },
1155 { TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0 },
1156 { TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0 },
1157 { TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0 },
1158 { TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 },
1159 { TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },
1160 { TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },
1161 { TEGRA114_CLK_VDE, TEGRA114_CLK_CLK_MAX, 600000000, 0 },
1162 { TEGRA114_CLK_SPDIF_IN_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1163 { TEGRA114_CLK_I2S0_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1164 { TEGRA114_CLK_I2S1_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1165 { TEGRA114_CLK_I2S2_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1166 { TEGRA114_CLK_I2S3_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1167 { TEGRA114_CLK_I2S4_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1168 { TEGRA114_CLK_VIMCLK_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1170 { TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },
1199 u32 select = 0; in tegra114_clock_tune_cpu_trimmers_high()
1222 u32 select = 0; in tegra114_clock_tune_cpu_trimmers_low()
1248 u32 dr = 0, r = 0; in tegra114_clock_tune_cpu_trimmers_init()
1306 clk_base = of_iomap(np, 0); in tegra114_clock_init()
1319 pmc_base = of_iomap(node, 0); in tegra114_clock_init()
1333 &pll_ref_freq) < 0) in tegra114_clock_init()