Lines Matching refs:con_id
935 { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
936 { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
937 { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
938 { .con_id = "osc", .dt_id = TEGRA124_CLK_OSC },
939 { .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },
940 { .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },
941 { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
942 { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
943 { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },
944 { .con_id = "pll_c3", .dt_id = TEGRA124_CLK_PLL_C3 },
945 { .con_id = "pll_p", .dt_id = TEGRA124_CLK_PLL_P },
946 { .con_id = "pll_p_out1", .dt_id = TEGRA124_CLK_PLL_P_OUT1 },
947 { .con_id = "pll_p_out2", .dt_id = TEGRA124_CLK_PLL_P_OUT2 },
948 { .con_id = "pll_p_out3", .dt_id = TEGRA124_CLK_PLL_P_OUT3 },
949 { .con_id = "pll_p_out4", .dt_id = TEGRA124_CLK_PLL_P_OUT4 },
950 { .con_id = "pll_m", .dt_id = TEGRA124_CLK_PLL_M },
951 { .con_id = "pll_m_out1", .dt_id = TEGRA124_CLK_PLL_M_OUT1 },
952 { .con_id = "pll_x", .dt_id = TEGRA124_CLK_PLL_X },
953 { .con_id = "pll_x_out0", .dt_id = TEGRA124_CLK_PLL_X_OUT0 },
954 { .con_id = "pll_u", .dt_id = TEGRA124_CLK_PLL_U },
955 { .con_id = "pll_u_480M", .dt_id = TEGRA124_CLK_PLL_U_480M },
956 { .con_id = "pll_u_60M", .dt_id = TEGRA124_CLK_PLL_U_60M },
957 { .con_id = "pll_u_48M", .dt_id = TEGRA124_CLK_PLL_U_48M },
958 { .con_id = "pll_u_12M", .dt_id = TEGRA124_CLK_PLL_U_12M },
959 { .con_id = "pll_d", .dt_id = TEGRA124_CLK_PLL_D },
960 { .con_id = "pll_d_out0", .dt_id = TEGRA124_CLK_PLL_D_OUT0 },
961 { .con_id = "pll_d2", .dt_id = TEGRA124_CLK_PLL_D2 },
962 { .con_id = "pll_d2_out0", .dt_id = TEGRA124_CLK_PLL_D2_OUT0 },
963 { .con_id = "pll_a", .dt_id = TEGRA124_CLK_PLL_A },
964 { .con_id = "pll_a_out0", .dt_id = TEGRA124_CLK_PLL_A_OUT0 },
965 { .con_id = "pll_re_vco", .dt_id = TEGRA124_CLK_PLL_RE_VCO },
966 { .con_id = "pll_re_out", .dt_id = TEGRA124_CLK_PLL_RE_OUT },
967 { .con_id = "spdif_in_sync", .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC },
968 { .con_id = "i2s0_sync", .dt_id = TEGRA124_CLK_I2S0_SYNC },
969 { .con_id = "i2s1_sync", .dt_id = TEGRA124_CLK_I2S1_SYNC },
970 { .con_id = "i2s2_sync", .dt_id = TEGRA124_CLK_I2S2_SYNC },
971 { .con_id = "i2s3_sync", .dt_id = TEGRA124_CLK_I2S3_SYNC },
972 { .con_id = "i2s4_sync", .dt_id = TEGRA124_CLK_I2S4_SYNC },
973 { .con_id = "vimclk_sync", .dt_id = TEGRA124_CLK_VIMCLK_SYNC },
974 { .con_id = "audio0", .dt_id = TEGRA124_CLK_AUDIO0 },
975 { .con_id = "audio1", .dt_id = TEGRA124_CLK_AUDIO1 },
976 { .con_id = "audio2", .dt_id = TEGRA124_CLK_AUDIO2 },
977 { .con_id = "audio3", .dt_id = TEGRA124_CLK_AUDIO3 },
978 { .con_id = "audio4", .dt_id = TEGRA124_CLK_AUDIO4 },
979 { .con_id = "spdif", .dt_id = TEGRA124_CLK_SPDIF },
980 { .con_id = "audio0_2x", .dt_id = TEGRA124_CLK_AUDIO0_2X },
981 { .con_id = "audio1_2x", .dt_id = TEGRA124_CLK_AUDIO1_2X },
982 { .con_id = "audio2_2x", .dt_id = TEGRA124_CLK_AUDIO2_2X },
983 { .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X },
984 { .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X },
985 { .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X },
986 { .con_id = "extern1", .dt_id = TEGRA124_CLK_EXTERN1 },
987 { .con_id = "extern2", .dt_id = TEGRA124_CLK_EXTERN2 },
988 { .con_id = "extern3", .dt_id = TEGRA124_CLK_EXTERN3 },
989 { .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G },
990 { .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP },
991 { .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },
992 { .con_id = "hclk", .dt_id = TEGRA124_CLK_HCLK },
993 { .con_id = "pclk", .dt_id = TEGRA124_CLK_PCLK },
994 { .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE },
997 { .con_id = "hda", .dt_id = TEGRA124_CLK_HDA },
998 { .con_id = "hda2codec_2x", .dt_id = TEGRA124_CLK_HDA2CODEC_2X },
999 { .con_id = "hda2hdmi", .dt_id = TEGRA124_CLK_HDA2HDMI },