Lines Matching refs:con_id
418 { .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C },
419 { .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 },
420 { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P },
421 { .con_id = "pll_p_out1", .dt_id = TEGRA20_CLK_PLL_P_OUT1 },
422 { .con_id = "pll_p_out2", .dt_id = TEGRA20_CLK_PLL_P_OUT2 },
423 { .con_id = "pll_p_out3", .dt_id = TEGRA20_CLK_PLL_P_OUT3 },
424 { .con_id = "pll_p_out4", .dt_id = TEGRA20_CLK_PLL_P_OUT4 },
425 { .con_id = "pll_m", .dt_id = TEGRA20_CLK_PLL_M },
426 { .con_id = "pll_m_out1", .dt_id = TEGRA20_CLK_PLL_M_OUT1 },
427 { .con_id = "pll_x", .dt_id = TEGRA20_CLK_PLL_X },
428 { .con_id = "pll_u", .dt_id = TEGRA20_CLK_PLL_U },
429 { .con_id = "pll_d", .dt_id = TEGRA20_CLK_PLL_D },
430 { .con_id = "pll_d_out0", .dt_id = TEGRA20_CLK_PLL_D_OUT0 },
431 { .con_id = "pll_a", .dt_id = TEGRA20_CLK_PLL_A },
432 { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 },
433 { .con_id = "pll_e", .dt_id = TEGRA20_CLK_PLL_E },
434 { .con_id = "cclk", .dt_id = TEGRA20_CLK_CCLK },
435 { .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK },
436 { .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK },
437 { .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK },
438 { .con_id = "fuse", .dt_id = TEGRA20_CLK_FUSE },
439 { .con_id = "twd", .dt_id = TEGRA20_CLK_TWD },
440 { .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO },
441 { .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X },
447 { .con_id = "csus", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSUS },
448 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP },
449 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA },
450 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV },
451 { .con_id = "emc", .dt_id = TEGRA20_CLK_EMC },
456 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSI },
457 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP },
458 { .con_id = "pex", .dt_id = TEGRA20_CLK_PEX },
459 { .con_id = "afi", .dt_id = TEGRA20_CLK_AFI },
460 { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
461 { .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
462 { .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
463 { .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },
464 { .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF },
467 { .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT },
468 { .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN },
484 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI },
498 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI_SENSOR },
500 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 },
501 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 },
502 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 },
503 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC },