93 	amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, &reg);  in f15h_select_dct()
96 	amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg);  in f15h_select_dct()
1186 		amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp);  in get_error_address()
1201 		amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp);  in get_error_address()
1242 	amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off,  &pvt->ranges[range].base.lo);  in read_dram_base_limit_regs()
1243 	amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo);  in read_dram_base_limit_regs()
1251 	amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off,  &pvt->ranges[range].base.hi);  in read_dram_base_limit_regs()
1252 	amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi);  in read_dram_base_limit_regs()
2013 	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg);  in f15_m30h_match_to_this_node()
2014 	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg);  in f15_m30h_match_to_this_node()
2092 		amd64_read_pci_cfg(pvt->F1,  in f15_m30h_match_to_this_node()
2720 	pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);  in reserve_mc_sibling_devs()
2721 	if (!pvt->F1) {  in reserve_mc_sibling_devs()
2729 		pci_dev_put(pvt->F1);  in reserve_mc_sibling_devs()
2730 		pvt->F1 = NULL;  in reserve_mc_sibling_devs()
2739 	edac_dbg(1, "F1: %s\n", pci_name(pvt->F1));  in reserve_mc_sibling_devs()
2752 		pci_dev_put(pvt->F1);  in free_mc_sibling_devs()
2872 	amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar);  in read_mc_regs()
3482 	if (pvt->F0 || pvt->F1)  in hw_info_put()