3828 	u32 reset_mask = 0;  in evergreen_gpu_check_soft_reset()  local
3838 		reset_mask |= RADEON_RESET_GFX;  in evergreen_gpu_check_soft_reset()
3842 		reset_mask |= RADEON_RESET_CP;  in evergreen_gpu_check_soft_reset()
3845 		reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;  in evergreen_gpu_check_soft_reset()
3850 		reset_mask |= RADEON_RESET_DMA;  in evergreen_gpu_check_soft_reset()
3855 		reset_mask |= RADEON_RESET_DMA;  in evergreen_gpu_check_soft_reset()
3860 		reset_mask |= RADEON_RESET_RLC;  in evergreen_gpu_check_soft_reset()
3863 		reset_mask |= RADEON_RESET_IH;  in evergreen_gpu_check_soft_reset()
3866 		reset_mask |= RADEON_RESET_SEM;  in evergreen_gpu_check_soft_reset()
3869 		reset_mask |= RADEON_RESET_GRBM;  in evergreen_gpu_check_soft_reset()
3872 		reset_mask |= RADEON_RESET_VMC;  in evergreen_gpu_check_soft_reset()
3876 		reset_mask |= RADEON_RESET_MC;  in evergreen_gpu_check_soft_reset()
3879 		reset_mask |= RADEON_RESET_DISPLAY;  in evergreen_gpu_check_soft_reset()
3884 		reset_mask |= RADEON_RESET_VMC;  in evergreen_gpu_check_soft_reset()
3887 	if (reset_mask & RADEON_RESET_MC) {  in evergreen_gpu_check_soft_reset()
3888 		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);  in evergreen_gpu_check_soft_reset()
3889 		reset_mask &= ~RADEON_RESET_MC;  in evergreen_gpu_check_soft_reset()
3892 	return reset_mask;  in evergreen_gpu_check_soft_reset()
3895 static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)  in evergreen_gpu_soft_reset()  argument
3901 	if (reset_mask == 0)  in evergreen_gpu_soft_reset()
3904 	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);  in evergreen_gpu_soft_reset()
3911 	if (reset_mask & RADEON_RESET_DMA) {  in evergreen_gpu_soft_reset()
3925 	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {  in evergreen_gpu_soft_reset()
3939 	if (reset_mask & RADEON_RESET_CP) {  in evergreen_gpu_soft_reset()
3946 	if (reset_mask & RADEON_RESET_DMA)  in evergreen_gpu_soft_reset()
3949 	if (reset_mask & RADEON_RESET_DISPLAY)  in evergreen_gpu_soft_reset()
3952 	if (reset_mask & RADEON_RESET_RLC)  in evergreen_gpu_soft_reset()
3955 	if (reset_mask & RADEON_RESET_SEM)  in evergreen_gpu_soft_reset()
3958 	if (reset_mask & RADEON_RESET_IH)  in evergreen_gpu_soft_reset()
3961 	if (reset_mask & RADEON_RESET_GRBM)  in evergreen_gpu_soft_reset()
3964 	if (reset_mask & RADEON_RESET_VMC)  in evergreen_gpu_soft_reset()
3968 		if (reset_mask & RADEON_RESET_MC)  in evergreen_gpu_soft_reset()
4053 	u32 reset_mask;  in evergreen_asic_reset()  local
4060 	reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_asic_reset()
4062 	if (reset_mask)  in evergreen_asic_reset()
4066 	evergreen_gpu_soft_reset(rdev, reset_mask);  in evergreen_asic_reset()
4068 	reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_asic_reset()
4071 	if (reset_mask && radeon_hard_reset)  in evergreen_asic_reset()
4074 	reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_asic_reset()
4076 	if (!reset_mask)  in evergreen_asic_reset()
4093 	u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_gfx_is_lockup()  local
4095 	if (!(reset_mask & (RADEON_RESET_GFX |  in evergreen_gfx_is_lockup()