2696 	radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));  in r600_cp_start()
2841 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));  in r600_ring_test()
2879 		radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));  in r600_fence_ring_emit()
2885 		radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));  in r600_fence_ring_emit()
2893 		radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));  in r600_fence_ring_emit()
2898 		radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));  in r600_fence_ring_emit()
2901 		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));  in r600_fence_ring_emit()
2905 		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));  in r600_fence_ring_emit()
2936 	radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));  in r600_semaphore_ring_emit()
2943 		radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));  in r600_semaphore_ring_emit()
2990 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));  in r600_copy_cpdma()
3001 		radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));  in r600_copy_cpdma()
3010 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));  in r600_copy_cpdma()
3376 		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));  in r600_ring_ib_execute()
3382 		radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));  in r600_ring_ib_execute()
3389 	radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));  in r600_ring_ib_execute()
3418 	ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);  in r600_ib_test()