Lines Matching refs:WREG32
126 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); in r600_rcu_rreg()
137 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); in r600_rcu_wreg()
138 WREG32(R600_RCU_DATA, (v)); in r600_rcu_wreg()
148 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); in r600_uvd_ctx_rreg()
159 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); in r600_uvd_ctx_wreg()
160 WREG32(R600_UVD_CTX_DATA, (v)); in r600_uvd_ctx_wreg()
346 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
873 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_hpd_set_polarity()
881 WREG32(DC_HPD2_INT_CONTROL, tmp); in r600_hpd_set_polarity()
889 WREG32(DC_HPD3_INT_CONTROL, tmp); in r600_hpd_set_polarity()
897 WREG32(DC_HPD4_INT_CONTROL, tmp); in r600_hpd_set_polarity()
905 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_hpd_set_polarity()
914 WREG32(DC_HPD6_INT_CONTROL, tmp); in r600_hpd_set_polarity()
927 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); in r600_hpd_set_polarity()
935 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); in r600_hpd_set_polarity()
943 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); in r600_hpd_set_polarity()
975 WREG32(DC_HPD1_CONTROL, tmp); in r600_hpd_init()
978 WREG32(DC_HPD2_CONTROL, tmp); in r600_hpd_init()
981 WREG32(DC_HPD3_CONTROL, tmp); in r600_hpd_init()
984 WREG32(DC_HPD4_CONTROL, tmp); in r600_hpd_init()
988 WREG32(DC_HPD5_CONTROL, tmp); in r600_hpd_init()
991 WREG32(DC_HPD6_CONTROL, tmp); in r600_hpd_init()
999 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); in r600_hpd_init()
1002 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); in r600_hpd_init()
1005 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); in r600_hpd_init()
1029 WREG32(DC_HPD1_CONTROL, 0); in r600_hpd_fini()
1032 WREG32(DC_HPD2_CONTROL, 0); in r600_hpd_fini()
1035 WREG32(DC_HPD3_CONTROL, 0); in r600_hpd_fini()
1038 WREG32(DC_HPD4_CONTROL, 0); in r600_hpd_fini()
1042 WREG32(DC_HPD5_CONTROL, 0); in r600_hpd_fini()
1045 WREG32(DC_HPD6_CONTROL, 0); in r600_hpd_fini()
1053 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); in r600_hpd_fini()
1056 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); in r600_hpd_fini()
1059 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); in r600_hpd_fini()
1090 WREG32(HDP_DEBUG1, 0); in r600_pcie_gart_tlb_flush()
1093 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); in r600_pcie_gart_tlb_flush()
1095 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_tlb_flush()
1096 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); in r600_pcie_gart_tlb_flush()
1097 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); in r600_pcie_gart_tlb_flush()
1143 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in r600_pcie_gart_enable()
1146 WREG32(VM_L2_CNTL2, 0); in r600_pcie_gart_enable()
1147 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); in r600_pcie_gart_enable()
1153 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); in r600_pcie_gart_enable()
1154 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); in r600_pcie_gart_enable()
1155 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); in r600_pcie_gart_enable()
1156 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); in r600_pcie_gart_enable()
1157 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); in r600_pcie_gart_enable()
1158 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); in r600_pcie_gart_enable()
1159 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); in r600_pcie_gart_enable()
1160 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); in r600_pcie_gart_enable()
1161 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); in r600_pcie_gart_enable()
1162 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); in r600_pcie_gart_enable()
1163 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); in r600_pcie_gart_enable()
1164 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); in r600_pcie_gart_enable()
1165 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); in r600_pcie_gart_enable()
1166 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); in r600_pcie_gart_enable()
1167 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); in r600_pcie_gart_enable()
1168 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); in r600_pcie_gart_enable()
1169 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_enable()
1170 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in r600_pcie_gart_enable()
1171 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in r600_pcie_gart_enable()
1172 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in r600_pcie_gart_enable()
1174 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, in r600_pcie_gart_enable()
1177 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in r600_pcie_gart_enable()
1194 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in r600_pcie_gart_disable()
1197 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | in r600_pcie_gart_disable()
1199 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); in r600_pcie_gart_disable()
1203 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); in r600_pcie_gart_disable()
1204 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); in r600_pcie_gart_disable()
1205 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); in r600_pcie_gart_disable()
1206 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); in r600_pcie_gart_disable()
1207 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); in r600_pcie_gart_disable()
1208 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); in r600_pcie_gart_disable()
1209 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); in r600_pcie_gart_disable()
1210 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); in r600_pcie_gart_disable()
1211 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); in r600_pcie_gart_disable()
1212 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); in r600_pcie_gart_disable()
1213 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); in r600_pcie_gart_disable()
1214 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); in r600_pcie_gart_disable()
1215 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); in r600_pcie_gart_disable()
1216 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); in r600_pcie_gart_disable()
1217 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); in r600_pcie_gart_disable()
1218 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); in r600_pcie_gart_disable()
1235 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in r600_agp_enable()
1238 WREG32(VM_L2_CNTL2, 0); in r600_agp_enable()
1239 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); in r600_agp_enable()
1245 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); in r600_agp_enable()
1246 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); in r600_agp_enable()
1247 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); in r600_agp_enable()
1248 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); in r600_agp_enable()
1249 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); in r600_agp_enable()
1250 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); in r600_agp_enable()
1251 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); in r600_agp_enable()
1252 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); in r600_agp_enable()
1253 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); in r600_agp_enable()
1254 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); in r600_agp_enable()
1255 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); in r600_agp_enable()
1256 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); in r600_agp_enable()
1257 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); in r600_agp_enable()
1258 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); in r600_agp_enable()
1260 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in r600_agp_enable()
1284 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg)); in rs780_mc_rreg()
1286 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR); in rs780_mc_rreg()
1296 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) | in rs780_mc_wreg()
1298 WREG32(R_0028FC_MC_DATA, v); in rs780_mc_wreg()
1299 WREG32(R_0028F8_MC_INDEX, 0x7F); in rs780_mc_wreg()
1311 WREG32((0x2c14 + j), 0x00000000); in r600_mc_program()
1312 WREG32((0x2c18 + j), 0x00000000); in r600_mc_program()
1313 WREG32((0x2c1c + j), 0x00000000); in r600_mc_program()
1314 WREG32((0x2c20 + j), 0x00000000); in r600_mc_program()
1315 WREG32((0x2c24 + j), 0x00000000); in r600_mc_program()
1317 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); in r600_mc_program()
1324 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); in r600_mc_program()
1329 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in r600_mc_program()
1331 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in r600_mc_program()
1335 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in r600_mc_program()
1337 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in r600_mc_program()
1341 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); in r600_mc_program()
1342 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); in r600_mc_program()
1344 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in r600_mc_program()
1347 WREG32(MC_VM_FB_LOCATION, tmp); in r600_mc_program()
1348 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in r600_mc_program()
1349 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); in r600_mc_program()
1350 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); in r600_mc_program()
1352 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); in r600_mc_program()
1353 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); in r600_mc_program()
1354 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in r600_mc_program()
1356 WREG32(MC_VM_AGP_BASE, 0); in r600_mc_program()
1357 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); in r600_mc_program()
1358 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); in r600_mc_program()
1564 WREG32(R600_BIOS_3_SCRATCH, tmp); in r600_set_bios_scratch_engine_hung()
1700 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); in r600_gpu_soft_reset()
1702 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); in r600_gpu_soft_reset()
1705 WREG32(RLC_CNTL, 0); in r600_gpu_soft_reset()
1711 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_soft_reset()
1788 WREG32(R_008020_GRBM_SOFT_RESET, tmp); in r600_gpu_soft_reset()
1794 WREG32(R_008020_GRBM_SOFT_RESET, tmp); in r600_gpu_soft_reset()
1802 WREG32(SRBM_SOFT_RESET, tmp); in r600_gpu_soft_reset()
1808 WREG32(SRBM_SOFT_RESET, tmp); in r600_gpu_soft_reset()
1832 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); in r600_gpu_pci_config_reset()
1834 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); in r600_gpu_pci_config_reset()
1837 WREG32(RLC_CNTL, 0); in r600_gpu_pci_config_reset()
1842 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_pci_config_reset()
1860 WREG32(BUS_CNTL, tmp); in r600_gpu_pci_config_reset()
1870 WREG32(SRBM_SOFT_RESET, tmp); in r600_gpu_pci_config_reset()
1872 WREG32(SRBM_SOFT_RESET, 0); in r600_gpu_pci_config_reset()
2077 WREG32((0x2c14 + j), 0x00000000); in r600_gpu_init()
2078 WREG32((0x2c18 + j), 0x00000000); in r600_gpu_init()
2079 WREG32((0x2c1c + j), 0x00000000); in r600_gpu_init()
2080 WREG32((0x2c20 + j), 0x00000000); in r600_gpu_init()
2081 WREG32((0x2c24 + j), 0x00000000); in r600_gpu_init()
2084 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); in r600_gpu_init()
2141 WREG32(GB_TILING_CONFIG, tiling_config); in r600_gpu_init()
2142 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); in r600_gpu_init()
2143 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); in r600_gpu_init()
2144 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); in r600_gpu_init()
2147 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); in r600_gpu_init()
2148 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); in r600_gpu_init()
2151 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); in r600_gpu_init()
2152 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); in r600_gpu_init()
2154 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | in r600_gpu_init()
2158 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); in r600_gpu_init()
2164 WREG32(SX_DEBUG_1, tmp); in r600_gpu_init()
2172 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); in r600_gpu_init()
2174 WREG32(DB_DEBUG, 0); in r600_gpu_init()
2176 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | in r600_gpu_init()
2179 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); in r600_gpu_init()
2180 WREG32(VGT_NUM_INSTANCES, 0); in r600_gpu_init()
2182 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); in r600_gpu_init()
2183 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); in r600_gpu_init()
2199 WREG32(SQ_MS_FIFO_SIZES, tmp); in r600_gpu_init()
2281 WREG32(SQ_CONFIG, sq_config); in r600_gpu_init()
2282 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); in r600_gpu_init()
2283 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); in r600_gpu_init()
2284 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); in r600_gpu_init()
2285 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); in r600_gpu_init()
2286 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); in r600_gpu_init()
2292 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); in r600_gpu_init()
2294 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); in r600_gpu_init()
2298 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | in r600_gpu_init()
2300 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | in r600_gpu_init()
2304 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | in r600_gpu_init()
2308 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | in r600_gpu_init()
2313 WREG32(VGT_STRMOUT_EN, 0); in r600_gpu_init()
2331 WREG32(VGT_ES_PER_GS, 128); in r600_gpu_init()
2332 WREG32(VGT_GS_PER_ES, tmp); in r600_gpu_init()
2333 WREG32(VGT_GS_PER_VS, 2); in r600_gpu_init()
2334 WREG32(VGT_GS_VERTEX_REUSE, 16); in r600_gpu_init()
2337 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); in r600_gpu_init()
2338 WREG32(VGT_STRMOUT_EN, 0); in r600_gpu_init()
2339 WREG32(SX_MISC, 0); in r600_gpu_init()
2340 WREG32(PA_SC_MODE_CNTL, 0); in r600_gpu_init()
2341 WREG32(PA_SC_AA_CONFIG, 0); in r600_gpu_init()
2342 WREG32(PA_SC_LINE_STIPPLE, 0); in r600_gpu_init()
2343 WREG32(SPI_INPUT_Z, 0); in r600_gpu_init()
2344 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); in r600_gpu_init()
2345 WREG32(CB_COLOR7_FRAG, 0); in r600_gpu_init()
2348 WREG32(CB_COLOR0_BASE, 0); in r600_gpu_init()
2349 WREG32(CB_COLOR1_BASE, 0); in r600_gpu_init()
2350 WREG32(CB_COLOR2_BASE, 0); in r600_gpu_init()
2351 WREG32(CB_COLOR3_BASE, 0); in r600_gpu_init()
2352 WREG32(CB_COLOR4_BASE, 0); in r600_gpu_init()
2353 WREG32(CB_COLOR5_BASE, 0); in r600_gpu_init()
2354 WREG32(CB_COLOR6_BASE, 0); in r600_gpu_init()
2355 WREG32(CB_COLOR7_BASE, 0); in r600_gpu_init()
2356 WREG32(CB_COLOR7_FRAG, 0); in r600_gpu_init()
2376 WREG32(TC_CNTL, tmp); in r600_gpu_init()
2379 WREG32(HDP_HOST_PATH_CNTL, tmp); in r600_gpu_init()
2383 WREG32(ARB_POP, tmp); in r600_gpu_init()
2385 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); in r600_gpu_init()
2386 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | in r600_gpu_init()
2388 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); in r600_gpu_init()
2389 WREG32(VC_ENHANCE, 0); in r600_gpu_init()
2402 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); in r600_pciep_rreg()
2414 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); in r600_pciep_wreg()
2416 WREG32(PCIE_PORT_DATA, (v)); in r600_pciep_wreg()
2428 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); in r600_cp_stop()
2429 WREG32(SCRATCH_UMSK, 0); in r600_cp_stop()
2639 WREG32(R600_CP_RB_WPTR, ring->wptr); in r600_gfx_set_wptr()
2653 WREG32(CP_RB_CNTL, in r600_cp_load_microcode()
2660 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); in r600_cp_load_microcode()
2663 WREG32(GRBM_SOFT_RESET, 0); in r600_cp_load_microcode()
2665 WREG32(CP_ME_RAM_WADDR, 0); in r600_cp_load_microcode()
2668 WREG32(CP_ME_RAM_WADDR, 0); in r600_cp_load_microcode()
2670 WREG32(CP_ME_RAM_DATA, in r600_cp_load_microcode()
2674 WREG32(CP_PFP_UCODE_ADDR, 0); in r600_cp_load_microcode()
2676 WREG32(CP_PFP_UCODE_DATA, in r600_cp_load_microcode()
2679 WREG32(CP_PFP_UCODE_ADDR, 0); in r600_cp_load_microcode()
2680 WREG32(CP_ME_RAM_WADDR, 0); in r600_cp_load_microcode()
2681 WREG32(CP_ME_RAM_RADDR, 0); in r600_cp_load_microcode()
2711 WREG32(R_0086D8_CP_ME_CNTL, cp_me); in r600_cp_start()
2723 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); in r600_cp_resume()
2726 WREG32(GRBM_SOFT_RESET, 0); in r600_cp_resume()
2734 WREG32(CP_RB_CNTL, tmp); in r600_cp_resume()
2735 WREG32(CP_SEM_WAIT_TIMER, 0x0); in r600_cp_resume()
2738 WREG32(CP_RB_WPTR_DELAY, 0); in r600_cp_resume()
2741 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); in r600_cp_resume()
2742 WREG32(CP_RB_RPTR_WR, 0); in r600_cp_resume()
2744 WREG32(CP_RB_WPTR, ring->wptr); in r600_cp_resume()
2747 WREG32(CP_RB_RPTR_ADDR, in r600_cp_resume()
2749 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in r600_cp_resume()
2750 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in r600_cp_resume()
2753 WREG32(SCRATCH_UMSK, 0xff); in r600_cp_resume()
2756 WREG32(SCRATCH_UMSK, 0); in r600_cp_resume()
2760 WREG32(CP_RB_CNTL, tmp); in r600_cp_resume()
2762 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); in r600_cp_resume()
2763 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); in r600_cp_resume()
2834 WREG32(scratch, 0xCAFEDEAD); in r600_ring_test()
3200 WREG32(CONFIG_CNTL, temp); in r600_vga_set_state()
3412 WREG32(scratch, 0xCAFEDEAD); in r600_ib_test()
3539 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); in r600_rlc_stop()
3542 WREG32(SRBM_SOFT_RESET, 0); in r600_rlc_stop()
3546 WREG32(RLC_CNTL, 0); in r600_rlc_stop()
3551 WREG32(RLC_CNTL, RLC_ENABLE); in r600_rlc_start()
3564 WREG32(RLC_HB_CNTL, 0); in r600_rlc_resume()
3566 WREG32(RLC_HB_BASE, 0); in r600_rlc_resume()
3567 WREG32(RLC_HB_RPTR, 0); in r600_rlc_resume()
3568 WREG32(RLC_HB_WPTR, 0); in r600_rlc_resume()
3569 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); in r600_rlc_resume()
3570 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); in r600_rlc_resume()
3571 WREG32(RLC_MC_CNTL, 0); in r600_rlc_resume()
3572 WREG32(RLC_UCODE_CNTL, 0); in r600_rlc_resume()
3577 WREG32(RLC_UCODE_ADDR, i); in r600_rlc_resume()
3578 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); in r600_rlc_resume()
3582 WREG32(RLC_UCODE_ADDR, i); in r600_rlc_resume()
3583 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); in r600_rlc_resume()
3586 WREG32(RLC_UCODE_ADDR, 0); in r600_rlc_resume()
3600 WREG32(IH_CNTL, ih_cntl); in r600_enable_interrupts()
3601 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_enable_interrupts()
3612 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_disable_interrupts()
3613 WREG32(IH_CNTL, ih_cntl); in r600_disable_interrupts()
3615 WREG32(IH_RB_RPTR, 0); in r600_disable_interrupts()
3616 WREG32(IH_RB_WPTR, 0); in r600_disable_interrupts()
3625 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in r600_disable_interrupt_state()
3627 WREG32(DMA_CNTL, tmp); in r600_disable_interrupt_state()
3628 WREG32(GRBM_INT_CNTL, 0); in r600_disable_interrupt_state()
3629 WREG32(DxMODE_INT_MASK, 0); in r600_disable_interrupt_state()
3630 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); in r600_disable_interrupt_state()
3631 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); in r600_disable_interrupt_state()
3633 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); in r600_disable_interrupt_state()
3634 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); in r600_disable_interrupt_state()
3636 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3638 WREG32(DC_HPD2_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3640 WREG32(DC_HPD3_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3642 WREG32(DC_HPD4_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3645 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3647 WREG32(DC_HPD6_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3649 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); in r600_disable_interrupt_state()
3651 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); in r600_disable_interrupt_state()
3654 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); in r600_disable_interrupt_state()
3656 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); in r600_disable_interrupt_state()
3659 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); in r600_disable_interrupt_state()
3660 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); in r600_disable_interrupt_state()
3662 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3664 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3666 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3668 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); in r600_disable_interrupt_state()
3670 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); in r600_disable_interrupt_state()
3700 WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8); in r600_irq_init()
3708 WREG32(INTERRUPT_CNTL, interrupt_cntl); in r600_irq_init()
3710 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in r600_irq_init()
3721 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); in r600_irq_init()
3722 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in r600_irq_init()
3724 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_irq_init()
3727 WREG32(IH_RB_RPTR, 0); in r600_irq_init()
3728 WREG32(IH_RB_WPTR, 0); in r600_irq_init()
3735 WREG32(IH_CNTL, ih_cntl); in r600_irq_init()
3876 WREG32(CP_INT_CNTL, cp_int_cntl); in r600_irq_set()
3877 WREG32(DMA_CNTL, dma_cntl); in r600_irq_set()
3878 WREG32(DxMODE_INT_MASK, mode_int); in r600_irq_set()
3879 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); in r600_irq_set()
3880 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); in r600_irq_set()
3881 WREG32(GRBM_INT_CNTL, grbm_int_cntl); in r600_irq_set()
3883 WREG32(DC_HPD1_INT_CONTROL, hpd1); in r600_irq_set()
3884 WREG32(DC_HPD2_INT_CONTROL, hpd2); in r600_irq_set()
3885 WREG32(DC_HPD3_INT_CONTROL, hpd3); in r600_irq_set()
3886 WREG32(DC_HPD4_INT_CONTROL, hpd4); in r600_irq_set()
3888 WREG32(DC_HPD5_INT_CONTROL, hpd5); in r600_irq_set()
3889 WREG32(DC_HPD6_INT_CONTROL, hpd6); in r600_irq_set()
3890 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); in r600_irq_set()
3891 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); in r600_irq_set()
3893 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); in r600_irq_set()
3894 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); in r600_irq_set()
3897 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); in r600_irq_set()
3898 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); in r600_irq_set()
3899 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); in r600_irq_set()
3900 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); in r600_irq_set()
3901 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); in r600_irq_set()
3904 WREG32(CG_THERMAL_INT, thermal_int); in r600_irq_set()
3906 WREG32(RV770_CG_THERMAL_INT, thermal_int); in r600_irq_set()
3941 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); in r600_irq_ack()
3943 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); in r600_irq_ack()
3945 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); in r600_irq_ack()
3947 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); in r600_irq_ack()
3949 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); in r600_irq_ack()
3951 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); in r600_irq_ack()
3956 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_irq_ack()
3960 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); in r600_irq_ack()
3967 WREG32(DC_HPD2_INT_CONTROL, tmp); in r600_irq_ack()
3971 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); in r600_irq_ack()
3978 WREG32(DC_HPD3_INT_CONTROL, tmp); in r600_irq_ack()
3982 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); in r600_irq_ack()
3988 WREG32(DC_HPD4_INT_CONTROL, tmp); in r600_irq_ack()
3994 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_irq_ack()
3999 WREG32(DC_HPD6_INT_CONTROL, tmp); in r600_irq_ack()
4004 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); in r600_irq_ack()
4009 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); in r600_irq_ack()
4015 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); in r600_irq_ack()
4021 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); in r600_irq_ack()
4025 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); in r600_irq_ack()
4060 WREG32(IH_RB_CNTL, tmp); in r600_get_ih_wptr()
4325 WREG32(IH_RB_RPTR, rptr); in r600_irq_process()
4395 WREG32(HDP_DEBUG1, 0); in r600_mmio_hdp_flush()
4398 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); in r600_mmio_hdp_flush()
4554 WREG32(MM_CFGREGS_CNTL, 0x8); in r600_pcie_gen2_enable()
4556 WREG32(MM_CFGREGS_CNTL, 0); in r600_pcie_gen2_enable()
4570 WREG32(0x541c, tmp | 0x8); in r600_pcie_gen2_enable()
4571 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); in r600_pcie_gen2_enable()
4576 WREG32(MM_CFGREGS_CNTL, 0); in r600_pcie_gen2_enable()
4618 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); in r600_get_gpu_clock_counter()