2719 	u32 rb_bufsz;  in r600_cp_resume()  local
2729 	rb_bufsz = order_base_2(ring->ring_size / 8);  in r600_cp_resume()
2730 	tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;  in r600_cp_resume()
2781 	u32 rb_bufsz;  in r600_ring_init()  local
2785 	rb_bufsz = order_base_2(ring_size / 8);  in r600_ring_init()
2786 	ring_size = (1 << (rb_bufsz + 1)) * 4;  in r600_ring_init()
3471 	u32 rb_bufsz;  in r600_ih_ring_init()  local
3474 	rb_bufsz = order_base_2(ring_size / 4);  in r600_ih_ring_init()
3475 	ring_size = (1 << rb_bufsz) * 4;  in r600_ih_ring_init()
3677 	int rb_bufsz;  in r600_irq_init()  local
3711 	rb_bufsz = order_base_2(rdev->ih.ring_size / 4);  in r600_irq_init()
3715 		      (rb_bufsz << 1));  in r600_irq_init()