Lines Matching refs:WREG32
120 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | in pre_xfer()
123 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | in pre_xfer()
134 WREG32(rec->mask_clk_reg, temp); in pre_xfer()
139 WREG32(rec->a_clk_reg, temp); in pre_xfer()
142 WREG32(rec->a_data_reg, temp); in pre_xfer()
146 WREG32(rec->en_clk_reg, temp); in pre_xfer()
149 WREG32(rec->en_data_reg, temp); in pre_xfer()
153 WREG32(rec->mask_clk_reg, temp); in pre_xfer()
157 WREG32(rec->mask_data_reg, temp); in pre_xfer()
172 WREG32(rec->mask_clk_reg, temp); in post_xfer()
176 WREG32(rec->mask_data_reg, temp); in post_xfer()
221 WREG32(rec->en_clk_reg, val); in set_clock()
234 WREG32(rec->en_data_reg, val); in set_data()
355 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); in r100_hw_i2c_xfer()
469 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | in r100_hw_i2c_xfer()
473 WREG32(i2c_data, (p->addr << 1) & 0xff); in r100_hw_i2c_xfer()
474 WREG32(i2c_data, 0); in r100_hw_i2c_xfer()
475 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | in r100_hw_i2c_xfer()
479 WREG32(i2c_cntl_0, reg); in r100_hw_i2c_xfer()
490 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); in r100_hw_i2c_xfer()
502 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | in r100_hw_i2c_xfer()
506 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); in r100_hw_i2c_xfer()
507 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | in r100_hw_i2c_xfer()
511 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); in r100_hw_i2c_xfer()
522 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); in r100_hw_i2c_xfer()
529 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | in r100_hw_i2c_xfer()
533 WREG32(i2c_data, (p->addr << 1) & 0xff); in r100_hw_i2c_xfer()
534 WREG32(i2c_data, p->buf[j]); in r100_hw_i2c_xfer()
535 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | in r100_hw_i2c_xfer()
539 WREG32(i2c_cntl_0, reg); in r100_hw_i2c_xfer()
550 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); in r100_hw_i2c_xfer()
560 WREG32(i2c_cntl_0, 0); in r100_hw_i2c_xfer()
561 WREG32(i2c_cntl_1, 0); in r100_hw_i2c_xfer()
562 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | in r100_hw_i2c_xfer()
570 WREG32(RADEON_BIOS_6_SCRATCH, tmp); in r100_hw_i2c_xfer()
603 WREG32(rec->mask_clk_reg, tmp); in r500_hw_i2c_xfer()
608 WREG32(rec->mask_data_reg, tmp); in r500_hw_i2c_xfer()
614 WREG32(rec->a_clk_reg, tmp); in r500_hw_i2c_xfer()
619 WREG32(rec->a_data_reg, tmp); in r500_hw_i2c_xfer()
625 WREG32(rec->en_clk_reg, tmp); in r500_hw_i2c_xfer()
630 WREG32(rec->en_data_reg, tmp); in r500_hw_i2c_xfer()
635 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); in r500_hw_i2c_xfer()
638 WREG32(0x494, saved2 | 0x1); in r500_hw_i2c_xfer()
640 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); in r500_hw_i2c_xfer()
672 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | in r500_hw_i2c_xfer()
675 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); in r500_hw_i2c_xfer()
677 WREG32(AVIVO_DC_I2C_RESET, 0); in r500_hw_i2c_xfer()
679 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); in r500_hw_i2c_xfer()
680 WREG32(AVIVO_DC_I2C_DATA, 0); in r500_hw_i2c_xfer()
682 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); in r500_hw_i2c_xfer()
683 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | in r500_hw_i2c_xfer()
686 WREG32(AVIVO_DC_I2C_CONTROL1, reg); in r500_hw_i2c_xfer()
687 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); in r500_hw_i2c_xfer()
698 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); in r500_hw_i2c_xfer()
716 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | in r500_hw_i2c_xfer()
719 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); in r500_hw_i2c_xfer()
721 WREG32(AVIVO_DC_I2C_RESET, 0); in r500_hw_i2c_xfer()
723 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); in r500_hw_i2c_xfer()
724 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); in r500_hw_i2c_xfer()
725 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | in r500_hw_i2c_xfer()
728 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); in r500_hw_i2c_xfer()
729 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); in r500_hw_i2c_xfer()
740 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); in r500_hw_i2c_xfer()
756 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | in r500_hw_i2c_xfer()
759 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); in r500_hw_i2c_xfer()
761 WREG32(AVIVO_DC_I2C_RESET, 0); in r500_hw_i2c_xfer()
763 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); in r500_hw_i2c_xfer()
765 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); in r500_hw_i2c_xfer()
767 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); in r500_hw_i2c_xfer()
768 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | in r500_hw_i2c_xfer()
771 WREG32(AVIVO_DC_I2C_CONTROL1, reg); in r500_hw_i2c_xfer()
772 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); in r500_hw_i2c_xfer()
783 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); in r500_hw_i2c_xfer()
795 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | in r500_hw_i2c_xfer()
798 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); in r500_hw_i2c_xfer()
800 WREG32(AVIVO_DC_I2C_RESET, 0); in r500_hw_i2c_xfer()
802 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); in r500_hw_i2c_xfer()
803 WREG32(AVIVO_DC_I2C_CONTROL1, saved1); in r500_hw_i2c_xfer()
804 WREG32(0x494, saved2); in r500_hw_i2c_xfer()
807 WREG32(RADEON_BIOS_6_SCRATCH, tmp); in r500_hw_i2c_xfer()