Lines Matching refs:WREG32
816 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
819 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in rv770_page_flip()
822 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
823 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
825 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
826 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
828 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
830 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
843 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
910 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable()
913 WREG32(VM_L2_CNTL2, 0); in rv770_pcie_gart_enable()
914 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_enable()
920 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); in rv770_pcie_gart_enable()
921 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); in rv770_pcie_gart_enable()
922 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); in rv770_pcie_gart_enable()
924 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); in rv770_pcie_gart_enable()
925 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); in rv770_pcie_gart_enable()
926 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); in rv770_pcie_gart_enable()
927 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); in rv770_pcie_gart_enable()
928 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); in rv770_pcie_gart_enable()
929 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in rv770_pcie_gart_enable()
930 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in rv770_pcie_gart_enable()
931 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in rv770_pcie_gart_enable()
932 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in rv770_pcie_gart_enable()
934 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, in rv770_pcie_gart_enable()
937 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in rv770_pcie_gart_enable()
954 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in rv770_pcie_gart_disable()
957 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | in rv770_pcie_gart_disable()
959 WREG32(VM_L2_CNTL2, 0); in rv770_pcie_gart_disable()
960 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_pcie_gart_disable()
963 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); in rv770_pcie_gart_disable()
964 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); in rv770_pcie_gart_disable()
965 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); in rv770_pcie_gart_disable()
966 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); in rv770_pcie_gart_disable()
967 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); in rv770_pcie_gart_disable()
968 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); in rv770_pcie_gart_disable()
969 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); in rv770_pcie_gart_disable()
987 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_agp_enable()
990 WREG32(VM_L2_CNTL2, 0); in rv770_agp_enable()
991 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in rv770_agp_enable()
997 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); in rv770_agp_enable()
998 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); in rv770_agp_enable()
999 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); in rv770_agp_enable()
1000 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); in rv770_agp_enable()
1001 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); in rv770_agp_enable()
1002 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); in rv770_agp_enable()
1003 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); in rv770_agp_enable()
1005 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in rv770_agp_enable()
1016 WREG32((0x2c14 + j), 0x00000000); in rv770_mc_program()
1017 WREG32((0x2c18 + j), 0x00000000); in rv770_mc_program()
1018 WREG32((0x2c1c + j), 0x00000000); in rv770_mc_program()
1019 WREG32((0x2c20 + j), 0x00000000); in rv770_mc_program()
1020 WREG32((0x2c24 + j), 0x00000000); in rv770_mc_program()
1032 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); in rv770_mc_program()
1037 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in rv770_mc_program()
1039 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in rv770_mc_program()
1043 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in rv770_mc_program()
1045 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in rv770_mc_program()
1049 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in rv770_mc_program()
1051 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in rv770_mc_program()
1054 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in rv770_mc_program()
1057 WREG32(MC_VM_FB_LOCATION, tmp); in rv770_mc_program()
1058 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in rv770_mc_program()
1059 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); in rv770_mc_program()
1060 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); in rv770_mc_program()
1062 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); in rv770_mc_program()
1063 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); in rv770_mc_program()
1064 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in rv770_mc_program()
1066 WREG32(MC_VM_AGP_BASE, 0); in rv770_mc_program()
1067 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); in rv770_mc_program()
1068 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); in rv770_mc_program()
1087 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); in r700_cp_stop()
1088 WREG32(SCRATCH_UMSK, 0); in r700_cp_stop()
1101 WREG32(CP_RB_CNTL, in rv770_cp_load_microcode()
1108 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); in rv770_cp_load_microcode()
1111 WREG32(GRBM_SOFT_RESET, 0); in rv770_cp_load_microcode()
1114 WREG32(CP_PFP_UCODE_ADDR, 0); in rv770_cp_load_microcode()
1116 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); in rv770_cp_load_microcode()
1117 WREG32(CP_PFP_UCODE_ADDR, 0); in rv770_cp_load_microcode()
1120 WREG32(CP_ME_RAM_WADDR, 0); in rv770_cp_load_microcode()
1122 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); in rv770_cp_load_microcode()
1124 WREG32(CP_PFP_UCODE_ADDR, 0); in rv770_cp_load_microcode()
1125 WREG32(CP_ME_RAM_WADDR, 0); in rv770_cp_load_microcode()
1126 WREG32(CP_ME_RAM_RADDR, 0); in rv770_cp_load_microcode()
1148 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in rv770_set_clk_bypass_mode()
1157 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in rv770_set_clk_bypass_mode()
1164 WREG32(MPLL_CNTL_MODE, tmp); in rv770_set_clk_bypass_mode()
1292 WREG32((0x2c14 + j), 0x00000000); in rv770_gpu_init()
1293 WREG32((0x2c18 + j), 0x00000000); in rv770_gpu_init()
1294 WREG32((0x2c1c + j), 0x00000000); in rv770_gpu_init()
1295 WREG32((0x2c20 + j), 0x00000000); in rv770_gpu_init()
1296 WREG32((0x2c24 + j), 0x00000000); in rv770_gpu_init()
1300 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); in rv770_gpu_init()
1314 WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1); in rv770_gpu_init()
1316 WREG32(SPI_CONFIG_CNTL, 0); in rv770_gpu_init()
1379 WREG32(GB_TILING_CONFIG, gb_tiling_config); in rv770_gpu_init()
1380 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); in rv770_gpu_init()
1381 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); in rv770_gpu_init()
1382 WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff)); in rv770_gpu_init()
1383 WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff)); in rv770_gpu_init()
1385 WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff)); in rv770_gpu_init()
1386 WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff)); in rv770_gpu_init()
1387 WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff)); in rv770_gpu_init()
1390 WREG32(CGTS_SYS_TCC_DISABLE, 0); in rv770_gpu_init()
1391 WREG32(CGTS_TCC_DISABLE, 0); in rv770_gpu_init()
1392 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); in rv770_gpu_init()
1393 WREG32(CGTS_USER_TCC_DISABLE, 0); in rv770_gpu_init()
1397 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); in rv770_gpu_init()
1398 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); in rv770_gpu_init()
1401 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | in rv770_gpu_init()
1404 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); in rv770_gpu_init()
1407 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO); in rv770_gpu_init()
1411 WREG32(SX_DEBUG_1, sx_debug_1); in rv770_gpu_init()
1416 WREG32(SMX_DC_CTL0, smx_dc_ctl0); in rv770_gpu_init()
1419 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | in rv770_gpu_init()
1425 WREG32(SMX_SAR_CTL0, 0x00003f3f); in rv770_gpu_init()
1440 WREG32(DB_DEBUG3, db_debug3); in rv770_gpu_init()
1445 WREG32(DB_DEBUG4, db_debug4); in rv770_gpu_init()
1448 …WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1)… in rv770_gpu_init()
1452 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | in rv770_gpu_init()
1456 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); in rv770_gpu_init()
1458 WREG32(VGT_NUM_INSTANCES, 1); in rv770_gpu_init()
1460 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); in rv770_gpu_init()
1462 WREG32(CP_PERFMON_CNTL, 0); in rv770_gpu_init()
1478 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); in rv770_gpu_init()
1499 WREG32(SQ_CONFIG, sq_config); in rv770_gpu_init()
1501 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | in rv770_gpu_init()
1505 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | in rv770_gpu_init()
1515 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); in rv770_gpu_init()
1517 …WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/… in rv770_gpu_init()
1520 …WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/… in rv770_gpu_init()
1528 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); in rv770_gpu_init()
1529 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); in rv770_gpu_init()
1530 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); in rv770_gpu_init()
1531 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); in rv770_gpu_init()
1532 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); in rv770_gpu_init()
1533 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); in rv770_gpu_init()
1534 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); in rv770_gpu_init()
1535 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); in rv770_gpu_init()
1537 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | in rv770_gpu_init()
1541 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | in rv770_gpu_init()
1544 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | in rv770_gpu_init()
1566 WREG32(VGT_ES_PER_GS, 128); in rv770_gpu_init()
1567 WREG32(VGT_GS_PER_ES, vgt_gs_per_es); in rv770_gpu_init()
1568 WREG32(VGT_GS_PER_VS, 2); in rv770_gpu_init()
1571 WREG32(VGT_GS_VERTEX_REUSE, 16); in rv770_gpu_init()
1572 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); in rv770_gpu_init()
1573 WREG32(VGT_STRMOUT_EN, 0); in rv770_gpu_init()
1574 WREG32(SX_MISC, 0); in rv770_gpu_init()
1575 WREG32(PA_SC_MODE_CNTL, 0); in rv770_gpu_init()
1576 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); in rv770_gpu_init()
1577 WREG32(PA_SC_AA_CONFIG, 0); in rv770_gpu_init()
1578 WREG32(PA_SC_CLIPRECT_RULE, 0xffff); in rv770_gpu_init()
1579 WREG32(PA_SC_LINE_STIPPLE, 0); in rv770_gpu_init()
1580 WREG32(SPI_INPUT_Z, 0); in rv770_gpu_init()
1581 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); in rv770_gpu_init()
1582 WREG32(CB_COLOR7_FRAG, 0); in rv770_gpu_init()
1585 WREG32(CB_COLOR0_BASE, 0); in rv770_gpu_init()
1586 WREG32(CB_COLOR1_BASE, 0); in rv770_gpu_init()
1587 WREG32(CB_COLOR2_BASE, 0); in rv770_gpu_init()
1588 WREG32(CB_COLOR3_BASE, 0); in rv770_gpu_init()
1589 WREG32(CB_COLOR4_BASE, 0); in rv770_gpu_init()
1590 WREG32(CB_COLOR5_BASE, 0); in rv770_gpu_init()
1591 WREG32(CB_COLOR6_BASE, 0); in rv770_gpu_init()
1592 WREG32(CB_COLOR7_BASE, 0); in rv770_gpu_init()
1594 WREG32(TCP_CNTL, 0); in rv770_gpu_init()
1597 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); in rv770_gpu_init()
1599 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); in rv770_gpu_init()
1601 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | in rv770_gpu_init()
1603 WREG32(VC_ENHANCE, 0); in rv770_gpu_init()
2071 WREG32(0x541c, tmp | 0x8); in rv770_pcie_gen2_enable()
2072 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); in rv770_pcie_gen2_enable()
2077 WREG32(MM_CFGREGS_CNTL, 0); in rv770_pcie_gen2_enable()