154 					     ASIC3_OFFSET(INTR, P_INT_STAT));  in asic3_irq_demux()
398 	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),  in asic3_irq_probe()
414 	asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),  in asic3_irq_probe()
614 		cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));  in asic3_clk_enable()
616 		asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);  in asic3_clk_enable()
630 		cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));  in asic3_clk_disable()
632 		asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);  in asic3_clk_disable()
667 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),  in ds1wm_enable()
670 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),  in ds1wm_enable()
673 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),  in ds1wm_enable()
684 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),  in ds1wm_disable()
743 	asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),  in asic3_mmc_enable()
745 	asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),  in asic3_mmc_enable()
747 	asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),  in asic3_mmc_enable()
749 	asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),  in asic3_mmc_enable()
760 	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),  in asic3_mmc_enable()
767 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),  in asic3_mmc_enable()
771 	asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),  in asic3_mmc_enable()
786 	asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),  in asic3_mmc_disable()
892 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),  in asic3_mfd_probe()
987 	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);  in asic3_probe()
1019 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),  in asic3_probe()
1040 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),  in asic3_remove()
1050 	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);  in asic3_remove()