204 	u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg);  member
368 	while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) {  in set_reset_mode()
401 	is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) &  in xcan_set_bittiming()
443 		   priv->read_reg(priv, XCAN_BRPR_OFFSET),  in xcan_set_bittiming()
444 		   priv->read_reg(priv, XCAN_BTR_OFFSET));  in xcan_set_bittiming()
508 		   priv->read_reg(priv, XCAN_SR_OFFSET));  in xcan_chip_start()
648 	if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) &  in xcan_start_xmit_fifo()
681 	if (unlikely(priv->read_reg(priv, XCAN_TRR_OFFSET) &  in xcan_start_xmit_mailbox()
757 	id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base));  in xcan_rx()
758 	dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base)) >>  in xcan_rx()
782 	data[0] = priv->read_reg(priv, XCAN_FRAME_DW1_OFFSET(frame_base));  in xcan_rx()
783 	data[1] = priv->read_reg(priv, XCAN_FRAME_DW2_OFFSET(frame_base));  in xcan_rx()
819 	id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base));  in xcanfd_rx()
820 	dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base));  in xcanfd_rx()
864 			data[0] = priv->read_reg(priv, dw_offset);  in xcanfd_rx()
871 			data[0] = priv->read_reg(priv, dw_offset + i);  in xcanfd_rx()
896 	u32 status = priv->read_reg(priv, XCAN_SR_OFFSET);  in xcan_current_error_state()
920 	u32 ecr = priv->read_reg(priv, XCAN_ECR_OFFSET);  in xcan_set_error_state()
995 	err_status = priv->read_reg(priv, XCAN_ESR_OFFSET);  in xcan_err_interrupt()
1106 		   __func__, priv->read_reg(priv, XCAN_ESR_OFFSET));  in xcan_err_interrupt()
1148 		fsr = priv->read_reg(priv, XCAN_FSR_OFFSET);  in xcan_rx_fifo_get_next_frame()
1168 		if (!(priv->read_reg(priv, XCAN_ISR_OFFSET) &  in xcan_rx_fifo_get_next_frame()
1223 		ier = priv->read_reg(priv, XCAN_IER_OFFSET);  in xcan_rx_poll()
1281 			isr = priv->read_reg(priv, XCAN_ISR_OFFSET);  in xcan_tx_interrupt()
1328 	isr = priv->read_reg(priv, XCAN_ISR_OFFSET);  in xcan_interrupt()
1354 		ier = priv->read_reg(priv, XCAN_IER_OFFSET);  in xcan_interrupt()
1486 	bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK;  in xcan_get_berr_counter()
1487 	bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) &  in xcan_get_berr_counter()
1795 	priv->read_reg = xcan_read_reg_le;  in xcan_probe()
1805 	if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) {  in xcan_probe()
1807 		priv->read_reg = xcan_read_reg_be;  in xcan_probe()