Lines Matching refs:adap
54 struct adapter *adap = mac->adapter; in xaui_serdes_reset() local
57 t3_write_reg(adap, ctrl, adap->params.vpd.xauicfg[macidx(mac)] | in xaui_serdes_reset()
61 t3_read_reg(adap, ctrl); in xaui_serdes_reset()
65 t3_set_reg_field(adap, ctrl, clear[i], 0); in xaui_serdes_reset()
99 struct adapter *adap = mac->adapter; in t3_mac_reset() local
102 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_); in t3_mac_reset()
103 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ in t3_mac_reset()
105 t3_write_regs(adap, mac_reset_avp, ARRAY_SIZE(mac_reset_avp), oft); in t3_mac_reset()
106 t3_set_reg_field(adap, A_XGM_RXFIFO_CFG + oft, in t3_mac_reset()
108 uses_xaui(adap) ? 0 : F_RXSTRFRWRD); in t3_mac_reset()
109 t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + oft, 0, F_UNDERUNFIX); in t3_mac_reset()
111 if (uses_xaui(adap)) { in t3_mac_reset()
112 if (adap->params.rev == 0) { in t3_mac_reset()
113 t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0, in t3_mac_reset()
115 if (t3_wait_op_done(adap, A_XGM_SERDES_STATUS1 + oft, in t3_mac_reset()
117 CH_ERR(adap, in t3_mac_reset()
122 t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0, in t3_mac_reset()
128 t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + oft, in t3_mac_reset()
133 if (is_10G(adap)) in t3_mac_reset()
135 else if (uses_xaui(adap)) in t3_mac_reset()
139 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val); in t3_mac_reset()
140 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ in t3_mac_reset()
141 if ((val & F_PCS_RESET_) && adap->params.rev) { in t3_mac_reset()
152 struct adapter *adap = mac->adapter; in t3b2_mac_reset() local
158 t3_set_reg_field(adap, A_MPS_CFG, F_PORT0ACTIVE, 0); in t3b2_mac_reset()
160 t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE, 0); in t3b2_mac_reset()
163 t3_set_reg_field(adap, A_MPS_CFG, F_ENFORCEPKT, 0); in t3b2_mac_reset()
165 t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN, 0); in t3b2_mac_reset()
167 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_); in t3b2_mac_reset()
168 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ in t3b2_mac_reset()
171 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx); in t3b2_mac_reset()
172 store = t3_read_reg(adap, A_TP_TX_DROP_CFG_CH0 + idx); in t3b2_mac_reset()
177 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx); in t3b2_mac_reset()
178 t3_write_reg(adap, A_TP_PIO_DATA, 0xc0000011); in t3b2_mac_reset()
182 if (t3_wait_op_done(adap, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT + oft, in t3b2_mac_reset()
184 CH_ERR(adap, "MAC %d Rx fifo drain failed\n", in t3b2_mac_reset()
189 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, 0); in t3b2_mac_reset()
190 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ in t3b2_mac_reset()
193 if (is_10G(adap)) in t3b2_mac_reset()
195 else if (uses_xaui(adap)) in t3b2_mac_reset()
199 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val); in t3b2_mac_reset()
200 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ in t3b2_mac_reset()
201 if ((val & F_PCS_RESET_) && adap->params.rev) { in t3b2_mac_reset()
205 t3_write_reg(adap, A_XGM_RX_CFG + oft, in t3b2_mac_reset()
210 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx); in t3b2_mac_reset()
211 t3_write_reg(adap, A_TP_PIO_DATA, store); in t3b2_mac_reset()
214 t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT0ACTIVE); in t3b2_mac_reset()
216 t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT1ACTIVE); in t3b2_mac_reset()
219 t3_set_reg_field(adap, A_MPS_CFG, F_ENFORCEPKT, 1); in t3b2_mac_reset()
222 t3_set_reg_field(adap, A_MPS_CFG, F_ENFORCEPKT, 1); in t3b2_mac_reset()
303 struct adapter *adap = mac->adapter; in t3_mac_set_rx_mode() local
306 val = t3_read_reg(adap, A_XGM_RX_CFG + oft) & ~F_COPYALLFRAMES; in t3_mac_set_rx_mode()
309 t3_write_reg(adap, A_XGM_RX_CFG + oft, val); in t3_mac_set_rx_mode()
332 t3_write_reg(adap, A_XGM_RX_HASH_LOW + oft, hash_lo); in t3_mac_set_rx_mode()
333 t3_write_reg(adap, A_XGM_RX_HASH_HIGH + oft, hash_hi); in t3_mac_set_rx_mode()
350 struct adapter *adap = mac->adapter; in t3_mac_set_mtu() local
362 t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu); in t3_mac_set_mtu()
364 if (adap->params.rev >= T3_REV_B2 && in t3_mac_set_mtu()
365 (t3_read_reg(adap, A_XGM_RX_CTRL + mac->offset) & F_RXEN)) { in t3_mac_set_mtu()
367 v = t3_read_reg(adap, A_XGM_RX_CFG + mac->offset); in t3_mac_set_mtu()
368 t3_set_reg_field(adap, A_XGM_RX_CFG + mac->offset, in t3_mac_set_mtu()
371 reg = adap->params.rev == T3_REV_B2 ? in t3_mac_set_mtu()
375 if (t3_wait_op_done(adap, reg + mac->offset, in t3_mac_set_mtu()
377 t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v); in t3_mac_set_mtu()
381 t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, in t3_mac_set_mtu()
384 t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v); in t3_mac_set_mtu()
387 t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, in t3_mac_set_mtu()
397 v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset); in t3_mac_set_mtu()
404 t3_write_reg(adap, A_XGM_RXFIFO_CFG + mac->offset, v); in t3_mac_set_mtu()
407 thres = (adap->params.vpd.cclk * 1000) / 15625; in t3_mac_set_mtu()
409 if (is_10G(adap)) in t3_mac_set_mtu()
413 ipg = (adap->params.rev == T3_REV_C) ? 0 : 1; in t3_mac_set_mtu()
414 t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset, in t3_mac_set_mtu()
418 if (adap->params.rev > 0) { in t3_mac_set_mtu()
419 divisor = (adap->params.rev == T3_REV_C) ? 64 : 8; in t3_mac_set_mtu()
420 t3_write_reg(adap, A_XGM_PAUSE_TIMER + mac->offset, in t3_mac_set_mtu()
423 t3_write_reg(adap, A_XGM_TX_PAUSE_QUANTA + mac->offset, in t3_mac_set_mtu()
431 struct adapter *adap = mac->adapter; in t3_mac_set_speed_duplex_fc() local
448 t3_set_reg_field(adap, A_XGM_PORT_CFG + oft, in t3_mac_set_speed_duplex_fc()
452 val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft); in t3_mac_set_speed_duplex_fc()
456 G_RXMAXPKTSIZE(t3_read_reg(adap, in t3_mac_set_speed_duplex_fc()
460 t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val); in t3_mac_set_speed_duplex_fc()
462 t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN, in t3_mac_set_speed_duplex_fc()
470 struct adapter *adap = mac->adapter; in t3_mac_enable() local
475 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx); in t3_mac_enable()
476 t3_write_reg(adap, A_TP_PIO_DATA, in t3_mac_enable()
477 adap->params.rev == T3_REV_C ? in t3_mac_enable()
479 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE); in t3_mac_enable()
480 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, in t3_mac_enable()
481 adap->params.rev == T3_REV_C ? 0 : 1 << idx); in t3_mac_enable()
483 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN); in t3_mac_enable()
485 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + idx); in t3_mac_enable()
487 mac->tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap, in t3_mac_enable()
489 mac->tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap, in t3_mac_enable()
494 mac->rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap, in t3_mac_enable()
502 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN); in t3_mac_enable()
508 struct adapter *adap = mac->adapter; in t3_mac_disable() local
511 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0); in t3_mac_disable()
520 t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0); in t3_mac_disable()
521 if (is_10G(adap)) in t3_mac_disable()
523 else if (uses_xaui(adap)) in t3_mac_disable()
534 struct adapter *adap = mac->adapter; in t3b2_mac_watchdog_task() local
544 tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap, in t3b2_mac_watchdog_task()
548 t3_write_reg(adap, A_TP_PIO_ADDR, in t3b2_mac_watchdog_task()
550 tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap, in t3b2_mac_watchdog_task()
579 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0); in t3b2_mac_watchdog_task()
580 t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */ in t3b2_mac_watchdog_task()
581 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, mac->txen); in t3b2_mac_watchdog_task()
582 t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */ in t3b2_mac_watchdog_task()