327 		dev_err(dev, "cannot enable regulators\n");  in qcom_pcie_init_2_1_0()
333 		dev_err(dev, "cannot deassert ahb reset\n");  in qcom_pcie_init_2_1_0()
339 		dev_err(dev, "cannot deassert ext reset\n");  in qcom_pcie_init_2_1_0()
345 		dev_err(dev, "cannot deassert phy reset\n");  in qcom_pcie_init_2_1_0()
351 		dev_err(dev, "cannot deassert pci reset\n");  in qcom_pcie_init_2_1_0()
357 		dev_err(dev, "cannot deassert por reset\n");  in qcom_pcie_init_2_1_0()
363 		dev_err(dev, "cannot deassert axi reset\n");  in qcom_pcie_init_2_1_0()
484 		dev_err(dev, "cannot deassert core reset\n");  in qcom_pcie_init_1_0_0()
490 		dev_err(dev, "cannot prepare/enable aux clock\n");  in qcom_pcie_init_1_0_0()
496 		dev_err(dev, "cannot prepare/enable iface clock\n");  in qcom_pcie_init_1_0_0()
502 		dev_err(dev, "cannot prepare/enable master_bus clock\n");  in qcom_pcie_init_1_0_0()
508 		dev_err(dev, "cannot prepare/enable slave_bus clock\n");  in qcom_pcie_init_1_0_0()
514 		dev_err(dev, "cannot enable vdda regulator\n");  in qcom_pcie_init_1_0_0()
616 		dev_err(dev, "cannot enable regulators\n");  in qcom_pcie_init_2_3_2()
622 		dev_err(dev, "cannot prepare/enable aux clock\n");  in qcom_pcie_init_2_3_2()
628 		dev_err(dev, "cannot prepare/enable cfg clock\n");  in qcom_pcie_init_2_3_2()
634 		dev_err(dev, "cannot prepare/enable master clock\n");  in qcom_pcie_init_2_3_2()
640 		dev_err(dev, "cannot prepare/enable slave clock\n");  in qcom_pcie_init_2_3_2()
689 		dev_err(dev, "cannot prepare/enable pipe clock\n");  in qcom_pcie_post_init_2_3_2()
805 		dev_err(dev, "cannot assert axi master reset\n");  in qcom_pcie_init_2_4_0()
811 		dev_err(dev, "cannot assert axi slave reset\n");  in qcom_pcie_init_2_4_0()
819 		dev_err(dev, "cannot assert pipe reset\n");  in qcom_pcie_init_2_4_0()
825 		dev_err(dev, "cannot assert pipe sticky reset\n");  in qcom_pcie_init_2_4_0()
831 		dev_err(dev, "cannot assert phy reset\n");  in qcom_pcie_init_2_4_0()
837 		dev_err(dev, "cannot assert phy ahb reset\n");  in qcom_pcie_init_2_4_0()
845 		dev_err(dev, "cannot assert axi master sticky reset\n");  in qcom_pcie_init_2_4_0()
851 		dev_err(dev, "cannot assert power reset\n");  in qcom_pcie_init_2_4_0()
857 		dev_err(dev, "cannot assert ahb reset\n");  in qcom_pcie_init_2_4_0()
865 		dev_err(dev, "cannot deassert phy ahb reset\n");  in qcom_pcie_init_2_4_0()
871 		dev_err(dev, "cannot deassert phy reset\n");  in qcom_pcie_init_2_4_0()
877 		dev_err(dev, "cannot deassert pipe reset\n");  in qcom_pcie_init_2_4_0()
883 		dev_err(dev, "cannot deassert pipe sticky reset\n");  in qcom_pcie_init_2_4_0()
891 		dev_err(dev, "cannot deassert axi master reset\n");  in qcom_pcie_init_2_4_0()
897 		dev_err(dev, "cannot deassert axi master sticky reset\n");  in qcom_pcie_init_2_4_0()
903 		dev_err(dev, "cannot deassert axi slave reset\n");  in qcom_pcie_init_2_4_0()
909 		dev_err(dev, "cannot deassert power reset\n");  in qcom_pcie_init_2_4_0()
915 		dev_err(dev, "cannot deassert ahb reset\n");  in qcom_pcie_init_2_4_0()
1055 		dev_err(dev, "cannot prepare/enable core clock\n");  in qcom_pcie_init_2_3_3()
1061 		dev_err(dev, "cannot prepare/enable core clock\n");  in qcom_pcie_init_2_3_3()
1067 		dev_err(dev, "cannot prepare/enable axi slave clock\n");  in qcom_pcie_init_2_3_3()
1073 		dev_err(dev, "cannot prepare/enable ahb clock\n");  in qcom_pcie_init_2_3_3()
1079 		dev_err(dev, "cannot prepare/enable aux clock\n");  in qcom_pcie_init_2_3_3()
1173 		dev_err(dev, "cannot enable regulators\n");  in qcom_pcie_init_2_7_0()
1183 		dev_err(dev, "cannot deassert pci reset\n");  in qcom_pcie_init_2_7_0()
1191 		dev_err(dev, "cannot deassert pci reset\n");  in qcom_pcie_init_2_7_0()
1197 		dev_err(dev, "cannot prepare/enable pipe clock\n");  in qcom_pcie_init_2_7_0()
1455 		dev_err(dev, "cannot initialize host\n");  in qcom_pcie_probe()