Lines Matching refs:bank
153 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, in stm32_gpio_backup_value() argument
156 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
157 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
160 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_mode() argument
163 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
165 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode()
166 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; in stm32_gpio_backup_mode()
169 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_driving() argument
172 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); in stm32_gpio_backup_driving()
173 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; in stm32_gpio_backup_driving()
176 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_speed() argument
179 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; in stm32_gpio_backup_speed()
180 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; in stm32_gpio_backup_speed()
183 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_bias() argument
186 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; in stm32_gpio_backup_bias()
187 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; in stm32_gpio_backup_bias()
192 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, in __stm32_gpio_set() argument
195 stm32_gpio_backup_value(bank, offset, value); in __stm32_gpio_set()
200 clk_enable(bank->clk); in __stm32_gpio_set()
202 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); in __stm32_gpio_set()
204 clk_disable(bank->clk); in __stm32_gpio_set()
209 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_request() local
210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_request()
212 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); in stm32_gpio_request()
230 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_get() local
233 clk_enable(bank->clk); in stm32_gpio_get()
235 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); in stm32_gpio_get()
237 clk_disable(bank->clk); in stm32_gpio_get()
244 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_set() local
246 __stm32_gpio_set(bank, offset, value); in stm32_gpio_set()
257 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_direction_output() local
259 __stm32_gpio_set(bank, offset, value); in stm32_gpio_direction_output()
268 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_to_irq() local
271 fwspec.fwnode = bank->fwnode; in stm32_gpio_to_irq()
281 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_get_direction() local
286 stm32_pmx_get_mode(bank, pin, &mode, &alt); in stm32_gpio_get_direction()
311 struct stm32_gpio_bank *bank = d->domain->host_data; in stm32_gpio_irq_trigger() local
315 level = stm32_gpio_get(&bank->gpio_chip, d->hwirq); in stm32_gpio_irq_trigger()
316 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || in stm32_gpio_irq_trigger()
317 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) in stm32_gpio_irq_trigger()
329 struct stm32_gpio_bank *bank = d->domain->host_data; in stm32_gpio_set_type() local
348 bank->irq_type[d->hwirq] = type; in stm32_gpio_set_type()
355 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_request_resources() local
356 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_irq_request_resources()
359 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
363 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
375 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_release_resources() local
377 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_release_resources()
415 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_activate() local
416 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_activate()
446 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); in stm32_gpio_domain_activate()
459 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_deactivate() local
460 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_deactivate()
472 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_alloc() local
484 bank); in stm32_gpio_domain_alloc()
744 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, in stm32_pmx_set_mode() argument
747 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pmx_set_mode()
754 clk_enable(bank->clk); in stm32_pmx_set_mode()
755 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_set_mode()
766 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_set_mode()
769 writel_relaxed(val, bank->base + alt_offset); in stm32_pmx_set_mode()
771 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
774 writel_relaxed(val, bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
779 stm32_gpio_backup_mode(bank, pin, mode, alt); in stm32_pmx_set_mode()
782 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_set_mode()
783 clk_disable(bank->clk); in stm32_pmx_set_mode()
788 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, in stm32_pmx_get_mode() argument
796 clk_enable(bank->clk); in stm32_pmx_get_mode()
797 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_get_mode()
799 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_get_mode()
803 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_get_mode()
807 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_get_mode()
808 clk_disable(bank->clk); in stm32_pmx_get_mode()
819 struct stm32_gpio_bank *bank; in stm32_pmx_set_mux() local
836 bank = gpiochip_get_data(range->gc); in stm32_pmx_set_mux()
842 return stm32_pmx_set_mode(bank, pin, mode, alt); in stm32_pmx_set_mux()
849 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); in stm32_pmx_gpio_set_direction() local
852 return stm32_pmx_set_mode(bank, pin, !input, 0); in stm32_pmx_gpio_set_direction()
866 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, in stm32_pconf_set_driving() argument
869 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_driving()
874 clk_enable(bank->clk); in stm32_pconf_set_driving()
875 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_driving()
886 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
889 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
894 stm32_gpio_backup_driving(bank, offset, drive); in stm32_pconf_set_driving()
897 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_driving()
898 clk_disable(bank->clk); in stm32_pconf_set_driving()
903 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, in stm32_pconf_get_driving() argument
909 clk_enable(bank->clk); in stm32_pconf_get_driving()
910 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_driving()
912 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_get_driving()
915 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_driving()
916 clk_disable(bank->clk); in stm32_pconf_get_driving()
921 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, in stm32_pconf_set_speed() argument
924 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_speed()
929 clk_enable(bank->clk); in stm32_pconf_set_speed()
930 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_speed()
941 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
944 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
949 stm32_gpio_backup_speed(bank, offset, speed); in stm32_pconf_set_speed()
952 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_speed()
953 clk_disable(bank->clk); in stm32_pconf_set_speed()
958 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, in stm32_pconf_get_speed() argument
964 clk_enable(bank->clk); in stm32_pconf_get_speed()
965 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_speed()
967 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_get_speed()
970 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_speed()
971 clk_disable(bank->clk); in stm32_pconf_get_speed()
976 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, in stm32_pconf_set_bias() argument
979 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_bias()
984 clk_enable(bank->clk); in stm32_pconf_set_bias()
985 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_bias()
996 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
999 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
1004 stm32_gpio_backup_bias(bank, offset, bias); in stm32_pconf_set_bias()
1007 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_bias()
1008 clk_disable(bank->clk); in stm32_pconf_set_bias()
1013 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, in stm32_pconf_get_bias() argument
1019 clk_enable(bank->clk); in stm32_pconf_get_bias()
1020 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_bias()
1022 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_get_bias()
1025 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_bias()
1026 clk_disable(bank->clk); in stm32_pconf_get_bias()
1031 static bool stm32_pconf_get(struct stm32_gpio_bank *bank, in stm32_pconf_get() argument
1037 clk_enable(bank->clk); in stm32_pconf_get()
1038 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get()
1041 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & in stm32_pconf_get()
1044 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & in stm32_pconf_get()
1047 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get()
1048 clk_disable(bank->clk); in stm32_pconf_get()
1059 struct stm32_gpio_bank *bank; in stm32_pconf_parse_conf() local
1068 bank = gpiochip_get_data(range->gc); in stm32_pconf_parse_conf()
1073 ret = stm32_pconf_set_driving(bank, offset, 0); in stm32_pconf_parse_conf()
1076 ret = stm32_pconf_set_driving(bank, offset, 1); in stm32_pconf_parse_conf()
1079 ret = stm32_pconf_set_speed(bank, offset, arg); in stm32_pconf_parse_conf()
1082 ret = stm32_pconf_set_bias(bank, offset, 0); in stm32_pconf_parse_conf()
1085 ret = stm32_pconf_set_bias(bank, offset, 1); in stm32_pconf_parse_conf()
1088 ret = stm32_pconf_set_bias(bank, offset, 2); in stm32_pconf_parse_conf()
1091 __stm32_gpio_set(bank, offset, arg); in stm32_pconf_parse_conf()
1155 struct stm32_gpio_bank *bank; in stm32_pconf_dbg_show() local
1170 bank = gpiochip_get_data(range->gc); in stm32_pconf_dbg_show()
1173 stm32_pmx_get_mode(bank, offset, &mode, &alt); in stm32_pconf_dbg_show()
1174 bias = stm32_pconf_get_bias(bank, offset); in stm32_pconf_dbg_show()
1181 val = stm32_pconf_get(bank, offset, true); in stm32_pconf_dbg_show()
1189 drive = stm32_pconf_get_driving(bank, offset); in stm32_pconf_dbg_show()
1190 speed = stm32_pconf_get_speed(bank, offset); in stm32_pconf_dbg_show()
1191 val = stm32_pconf_get(bank, offset, false); in stm32_pconf_dbg_show()
1201 drive = stm32_pconf_get_driving(bank, offset); in stm32_pconf_dbg_show()
1202 speed = stm32_pconf_get_speed(bank, offset); in stm32_pconf_dbg_show()
1225 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; in stm32_gpiolib_register_bank() local
1227 struct pinctrl_gpio_range *range = &bank->range; in stm32_gpiolib_register_bank()
1234 if (!IS_ERR(bank->rstc)) in stm32_gpiolib_register_bank()
1235 reset_control_deassert(bank->rstc); in stm32_gpiolib_register_bank()
1240 bank->base = devm_ioremap_resource(dev, &res); in stm32_gpiolib_register_bank()
1241 if (IS_ERR(bank->base)) in stm32_gpiolib_register_bank()
1242 return PTR_ERR(bank->base); in stm32_gpiolib_register_bank()
1244 err = clk_prepare(bank->clk); in stm32_gpiolib_register_bank()
1250 bank->gpio_chip = stm32_gpio_template; in stm32_gpiolib_register_bank()
1252 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1256 bank->gpio_chip.base = args.args[1]; in stm32_gpiolib_register_bank()
1264 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1265 range->name = bank->gpio_chip.label; in stm32_gpiolib_register_bank()
1270 range->gc = &bank->gpio_chip; in stm32_gpiolib_register_bank()
1278 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1280 bank->gpio_chip.ngpio = npins; in stm32_gpiolib_register_bank()
1281 bank->gpio_chip.of_node = np; in stm32_gpiolib_register_bank()
1282 bank->gpio_chip.parent = dev; in stm32_gpiolib_register_bank()
1283 bank->bank_nr = bank_nr; in stm32_gpiolib_register_bank()
1284 bank->bank_ioport_nr = bank_ioport_nr; in stm32_gpiolib_register_bank()
1285 spin_lock_init(&bank->lock); in stm32_gpiolib_register_bank()
1288 bank->fwnode = of_node_to_fwnode(np); in stm32_gpiolib_register_bank()
1290 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, in stm32_gpiolib_register_bank()
1291 STM32_GPIO_IRQ_LINE, bank->fwnode, in stm32_gpiolib_register_bank()
1292 &stm32_gpio_domain_ops, bank); in stm32_gpiolib_register_bank()
1294 if (!bank->domain) in stm32_gpiolib_register_bank()
1297 err = gpiochip_add_data(&bank->gpio_chip, bank); in stm32_gpiolib_register_bank()
1303 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1545 struct stm32_gpio_bank *bank = &pctl->banks[i]; in stm32_pctl_probe() local
1548 bank->rstc = of_reset_control_get_exclusive(child, in stm32_pctl_probe()
1550 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) in stm32_pctl_probe()
1553 bank->clk = of_clk_get_by_name(child, NULL); in stm32_pctl_probe()
1554 if (IS_ERR(bank->clk)) { in stm32_pctl_probe()
1555 if (PTR_ERR(bank->clk) != -EPROBE_DEFER) in stm32_pctl_probe()
1558 PTR_ERR(bank->clk)); in stm32_pctl_probe()
1559 return PTR_ERR(bank->clk); in stm32_pctl_probe()
1588 struct stm32_gpio_bank *bank; in stm32_pinctrl_restore_gpio_regs() local
1601 bank = gpiochip_get_data(range->gc); in stm32_pinctrl_restore_gpio_regs()
1603 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; in stm32_pinctrl_restore_gpio_regs()
1605 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; in stm32_pinctrl_restore_gpio_regs()
1608 ret = stm32_pmx_set_mode(bank, offset, mode, alt); in stm32_pinctrl_restore_gpio_regs()
1613 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); in stm32_pinctrl_restore_gpio_regs()
1615 __stm32_gpio_set(bank, offset, val); in stm32_pinctrl_restore_gpio_regs()
1618 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); in stm32_pinctrl_restore_gpio_regs()
1620 ret = stm32_pconf_set_driving(bank, offset, val); in stm32_pinctrl_restore_gpio_regs()
1624 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; in stm32_pinctrl_restore_gpio_regs()
1626 ret = stm32_pconf_set_speed(bank, offset, val); in stm32_pinctrl_restore_gpio_regs()
1630 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; in stm32_pinctrl_restore_gpio_regs()
1632 ret = stm32_pconf_set_bias(bank, offset, val); in stm32_pinctrl_restore_gpio_regs()
1637 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); in stm32_pinctrl_restore_gpio_regs()