Lines Matching +full:0 +full:x12345678

20 #define JZ_REG_RTC_CTRL		0x00
21 #define JZ_REG_RTC_SEC		0x04
22 #define JZ_REG_RTC_SEC_ALARM	0x08
23 #define JZ_REG_RTC_REGULATOR	0x0C
24 #define JZ_REG_RTC_HIBERNATE	0x20
25 #define JZ_REG_RTC_WAKEUP_FILTER	0x24
26 #define JZ_REG_RTC_RESET_COUNTER	0x28
27 #define JZ_REG_RTC_SCRATCHPAD	0x34
30 #define JZ_REG_RTC_WENR	0x3C
39 #define JZ_RTC_CTRL_ENABLE	BIT(0)
42 #define JZ_RTC_WENR_MAGIC	0xA55A
44 #define JZ_RTC_WAKEUP_FILTER_MASK	0x0000FFE0
45 #define JZ_RTC_RESET_COUNTER_MASK	0x00000FE0
78 	return timeout ? 0 : -EIO;  in jz4740_rtc_wait_write_ready()
87 	if (ret != 0)  in jz4780_rtc_enable_write()
96 	return timeout ? 0 : -EIO;  in jz4780_rtc_enable_write()
102 	int ret = 0;  in jz4740_rtc_reg_write()
106 	if (ret == 0)  in jz4740_rtc_reg_write()
108 	if (ret == 0)  in jz4740_rtc_reg_write()
146 	if (jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD) != 0x12345678)  in jz4740_rtc_read_time()
161 	if (timeout == 0)  in jz4740_rtc_read_time()
166 	return 0;  in jz4740_rtc_read_time()
178 	return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);  in jz4740_rtc_set_time()
196 	return 0;  in jz4740_rtc_read_alarm()
231 	unsigned long events = 0;  in jz4740_rtc_irq()
288 	 * Range is 0 to 2 sec if RTC is clocked at 32 kHz.  in jz4740_rtc_set_wakeup_params()
299 	 * Range is 0 to 125 ms if RTC is clocked at 32 kHz.  in jz4740_rtc_set_wakeup_params()
324 	irq = platform_get_irq(pdev, 0);  in jz4740_rtc_probe()
325 	if (irq < 0)  in jz4740_rtc_probe()
328 	rtc->base = devm_platform_ioremap_resource(pdev, 0);  in jz4740_rtc_probe()
382 	ret = devm_request_irq(dev, irq, jz4740_rtc_irq, 0,  in jz4740_rtc_probe()
398 	return 0;  in jz4740_rtc_probe()