Lines Matching refs:regVal
390 u32 regVal; in pm8001_bar4_shift() local
399 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW); in pm8001_bar4_shift()
400 } while ((regVal != shiftValue) && time_before(jiffies, start)); in pm8001_bar4_shift()
402 if (regVal != shiftValue) { in pm8001_bar4_shift()
405 regVal); in pm8001_bar4_shift()
759 u32 regVal, regVal1, regVal2; in soft_reset_ready_check() local
765 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) in soft_reset_ready_check()
767 if (regVal == SCRATCH_PAD2_FWRDY_RST) { in soft_reset_ready_check()
785 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) & in soft_reset_ready_check()
787 if (regVal != SCRATCH_PAD2_FWRDY_RST) { in soft_reset_ready_check()
814 u32 regVal, toggleVal; in pm8001_chip_soft_rst() local
836 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP); in pm8001_chip_soft_rst()
838 regVal); in pm8001_chip_soft_rst()
847 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1); in pm8001_chip_soft_rst()
849 regVal); in pm8001_chip_soft_rst()
852 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE); in pm8001_chip_soft_rst()
854 regVal); in pm8001_chip_soft_rst()
857 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT); in pm8001_chip_soft_rst()
859 regVal); in pm8001_chip_soft_rst()
860 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal); in pm8001_chip_soft_rst()
862 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE); in pm8001_chip_soft_rst()
864 regVal); in pm8001_chip_soft_rst()
867 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT); in pm8001_chip_soft_rst()
868 pm8001_dbg(pm8001_ha, INIT, "PCIE - Error Interrupt = 0x%x\n", regVal); in pm8001_chip_soft_rst()
869 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal); in pm8001_chip_soft_rst()
872 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) in pm8001_chip_soft_rst()
874 toggleVal = regVal ^ SCRATCH_PAD1_RST; in pm8001_chip_soft_rst()
893 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); in pm8001_chip_soft_rst()
902 regVal &= ~(0x00003b00); in pm8001_chip_soft_rst()
904 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); in pm8001_chip_soft_rst()
948 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET); in pm8001_chip_soft_rst()
950 regVal); in pm8001_chip_soft_rst()
952 regVal &= 0xFFFFFFFC; in pm8001_chip_soft_rst()
953 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); in pm8001_chip_soft_rst()
963 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
965 regVal); in pm8001_chip_soft_rst()
966 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); in pm8001_chip_soft_rst()
967 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
970 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
972 regVal); in pm8001_chip_soft_rst()
973 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); in pm8001_chip_soft_rst()
974 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
980 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
983 regVal); in pm8001_chip_soft_rst()
984 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); in pm8001_chip_soft_rst()
985 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
1001 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); in pm8001_chip_soft_rst()
1010 regVal |= (GSM_CONFIG_RESET_VALUE); in pm8001_chip_soft_rst()
1011 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); in pm8001_chip_soft_rst()
1016 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); in pm8001_chip_soft_rst()
1020 regVal); in pm8001_chip_soft_rst()
1025 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); in pm8001_chip_soft_rst()
1031 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); in pm8001_chip_soft_rst()
1045 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
1046 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); in pm8001_chip_soft_rst()
1047 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
1058 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & in pm8001_chip_soft_rst()
1060 } while ((regVal != toggleVal) && (--max_wait_count)); in pm8001_chip_soft_rst()
1063 regVal = pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1066 toggleVal, regVal); in pm8001_chip_soft_rst()
1091 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); in pm8001_chip_soft_rst()
1095 regVal); in pm8001_chip_soft_rst()
1096 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); in pm8001_chip_soft_rst()
1100 regVal); in pm8001_chip_soft_rst()
1123 u32 regVal; in pm8001_hw_chip_rst() local
1127 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); in pm8001_hw_chip_rst()
1128 regVal &= ~(SPC_REG_RESET_DEVICE); in pm8001_hw_chip_rst()
1129 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); in pm8001_hw_chip_rst()
1135 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); in pm8001_hw_chip_rst()
1136 regVal |= SPC_REG_RESET_DEVICE; in pm8001_hw_chip_rst()
1137 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); in pm8001_hw_chip_rst()