110 	int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);  member
197 	ret = ctrl->reg_write(ctrl, SWRM_CMD_FIFO_WR_CMD, val);  in qcom_swrm_cmd_fifo_wr_cmd()
230 	ret = ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val);  in qcom_swrm_cmd_fifo_rd_cmd()
286 		ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);  in qcom_swrm_irq_handler()
298 	ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, sts);  in qcom_swrm_irq_handler()
317 	ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);  in qcom_swrm_init()
320 	ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 0);  in qcom_swrm_init()
323 	ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,  in qcom_swrm_init()
329 	ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);  in qcom_swrm_init()
332 	ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, SWRM_RD_WR_CMD_RETRIES);  in qcom_swrm_init()
335 	ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,  in qcom_swrm_init()
341 		ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,  in qcom_swrm_init()
392 	return ctrl->reg_write(ctrl, reg, val);  in qcom_swrm_pre_bank_switch()
416 	ret = ctrl->reg_write(ctrl, reg, value);  in qcom_swrm_transport_params()
421 		ret = ctrl->reg_write(ctrl, reg, 1);  in qcom_swrm_transport_params()
442 	return ctrl->reg_write(ctrl, reg, val);  in qcom_swrm_port_enable()
808 		ctrl->reg_write = qcom_swrm_ahb_reg_write;
814 		ctrl->reg_write = qcom_swrm_cpu_reg_write;