Lines Matching refs:cr0
28 u32 cr0; member
268 u32 cr0 = 0; in dw_spi_prepare_cr0() local
272 cr0 |= SSI_MOTO_SPI << SPI_FRF_OFFSET; in dw_spi_prepare_cr0()
279 cr0 |= ((spi->mode & SPI_CPOL) ? 1 : 0) << SPI_SCOL_OFFSET; in dw_spi_prepare_cr0()
280 cr0 |= ((spi->mode & SPI_CPHA) ? 1 : 0) << SPI_SCPH_OFFSET; in dw_spi_prepare_cr0()
283 cr0 |= ((spi->mode & SPI_LOOP) ? 1 : 0) << SPI_SRL_OFFSET; in dw_spi_prepare_cr0()
286 cr0 |= SSI_MOTO_SPI << DWC_SSI_CTRLR0_FRF_OFFSET; in dw_spi_prepare_cr0()
293 cr0 |= ((spi->mode & SPI_CPOL) ? 1 : 0) << DWC_SSI_CTRLR0_SCPOL_OFFSET; in dw_spi_prepare_cr0()
294 cr0 |= ((spi->mode & SPI_CPHA) ? 1 : 0) << DWC_SSI_CTRLR0_SCPH_OFFSET; in dw_spi_prepare_cr0()
297 cr0 |= ((spi->mode & SPI_LOOP) ? 1 : 0) << DWC_SSI_CTRLR0_SRL_OFFSET; in dw_spi_prepare_cr0()
300 cr0 |= DWC_SSI_CTRLR0_KEEMBAY_MST; in dw_spi_prepare_cr0()
303 return cr0; in dw_spi_prepare_cr0()
310 u32 cr0 = chip->cr0; in dw_spi_update_config() local
315 cr0 |= (cfg->dfs - 1); in dw_spi_update_config()
319 cr0 |= cfg->tmode << SPI_TMOD_OFFSET; in dw_spi_update_config()
322 cr0 |= cfg->tmode << DWC_SSI_CTRLR0_TMOD_OFFSET; in dw_spi_update_config()
324 dw_writel(dws, DW_SPI_CTRLR0, cr0); in dw_spi_update_config()
795 chip->cr0 = dw_spi_prepare_cr0(dws, spi); in dw_spi_setup()