Lines Matching +full:fifo +full:- +full:depth +full:- +full:bits
1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/bits.h>
11 #include <linux/spi/spi-mem.h>
85 /* Bit fields in SR, 7 bits */
86 #define SR_MASK 0x7f /* cover 7 bits */
95 /* Bit fields in ISR, IMR, RISR, 7 bits */
150 u32 fifo_len; /* depth of the FIFO buffer */
151 u32 max_mem_freq; /* max mem-ops bus freq */
196 return __raw_readl(dws->regs + offset); in dw_readl()
201 __raw_writel(val, dws->regs + offset); in dw_writel()
206 switch (dws->reg_io_width) { in dw_read_io_reg()
208 return readw_relaxed(dws->regs + offset); in dw_read_io_reg()
211 return readl_relaxed(dws->regs + offset); in dw_read_io_reg()
217 switch (dws->reg_io_width) { in dw_write_io_reg()
219 writew_relaxed(val, dws->regs + offset); in dw_write_io_reg()
223 writel_relaxed(val, dws->regs + offset); in dw_write_io_reg()
238 /* Disable IRQ bits */
247 /* Enable IRQ bits */
258 * and CS, then re-enables the controller back. Transmit and receive FIFO