Lines Matching refs:se
67 struct geni_se se; member
98 ret = geni_se_clk_freq_match(&mas->se, in get_spi_clk_cfg()
126 struct geni_se *se = &mas->se; in handle_fifo_timeout() local
130 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in handle_fifo_timeout()
132 geni_se_cancel_m_cmd(se); in handle_fifo_timeout()
141 geni_se_abort_m_cmd(se); in handle_fifo_timeout()
158 struct geni_se *se = &mas->se; in spi_geni_is_abort_still_pending() local
171 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); in spi_geni_is_abort_still_pending()
172 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN); in spi_geni_is_abort_still_pending()
194 struct geni_se *se = &mas->se; in spi_geni_set_cs() local
215 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0); in spi_geni_set_cs()
217 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0); in spi_geni_set_cs()
233 struct geni_se *se = &mas->se; in spi_setup_word_len() local
244 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, in spi_setup_word_len()
247 writel(word_len, se->base + SE_SPI_WORD_LEN); in spi_setup_word_len()
254 struct geni_se *se = &mas->se; in geni_spi_set_clock_and_bw() local
277 writel(clk_sel, se->base + SE_GENI_CLK_SEL); in geni_spi_set_clock_and_bw()
278 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); in geni_spi_set_clock_and_bw()
281 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); in geni_spi_set_clock_and_bw()
282 ret = geni_icc_set_bw(se); in geni_spi_set_clock_and_bw()
293 struct geni_se *se = &mas->se; in setup_fifo_params() local
314 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK); in setup_fifo_params()
315 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL); in setup_fifo_params()
316 writel(cpha, se->base + SE_SPI_CPHA); in setup_fifo_params()
317 writel(cpol, se->base + SE_SPI_CPOL); in setup_fifo_params()
318 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV); in setup_fifo_params()
343 struct geni_se *se = &mas->se; in spi_geni_init() local
349 proto = geni_se_read_proto(se); in spi_geni_init()
355 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); in spi_geni_init()
358 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); in spi_geni_init()
364 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); in spi_geni_init()
367 ver = geni_se_get_qup_hw_version(se); in spi_geni_init()
376 geni_se_select_mode(se, GENI_SE_FIFO); in spi_geni_init()
379 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); in spi_geni_init()
381 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); in spi_geni_init()
403 struct geni_se *se = &mas->se; in geni_spi_handle_tx() local
411 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_handle_tx()
429 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); in geni_spi_handle_tx()
433 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_handle_tx()
441 struct geni_se *se = &mas->se; in geni_spi_handle_rx() local
449 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); in geni_spi_handle_rx()
461 readl(se->base + SE_GENI_RX_FIFOn); in geni_spi_handle_rx()
476 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); in geni_spi_handle_rx()
489 struct geni_se *se = &mas->se; in setup_fifo_xfer() local
530 writel(len, se->base + SE_SPI_TX_TRANS_LEN); in setup_fifo_xfer()
535 writel(len, se->base + SE_SPI_RX_TRANS_LEN); in setup_fifo_xfer()
544 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION); in setup_fifo_xfer()
553 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); in setup_fifo_xfer()
579 struct geni_se *se = &mas->se; in geni_spi_isr() local
582 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); in geni_spi_isr()
617 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_isr()
647 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); in geni_spi_isr()
683 mas->se.dev = dev; in spi_geni_probe()
684 mas->se.wrapper = dev_get_drvdata(dev->parent); in spi_geni_probe()
685 mas->se.base = base; in spi_geni_probe()
686 mas->se.clk = clk; in spi_geni_probe()
687 mas->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se"); in spi_geni_probe()
688 if (IS_ERR(mas->se.opp_table)) in spi_geni_probe()
689 return PTR_ERR(mas->se.opp_table); in spi_geni_probe()
717 ret = geni_icc_get(&mas->se, NULL); in spi_geni_probe()
721 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); in spi_geni_probe()
722 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; in spi_geni_probe()
724 ret = geni_icc_set_bw(&mas->se); in spi_geni_probe()
747 dev_pm_opp_put_clkname(mas->se.opp_table); in spi_geni_probe()
762 dev_pm_opp_put_clkname(mas->se.opp_table); in spi_geni_remove()
775 ret = geni_se_resources_off(&mas->se); in spi_geni_runtime_suspend()
779 return geni_icc_disable(&mas->se); in spi_geni_runtime_suspend()
788 ret = geni_icc_enable(&mas->se); in spi_geni_runtime_resume()
792 ret = geni_se_resources_on(&mas->se); in spi_geni_runtime_resume()