49 	u32 cycle;  member
57 	u32 cycle;  member
156 		dma_addr_t buf_base, u32 aspace, u32 cycle)  in fake_slave_set()  argument
213 	bridge->slaves[i].cycle = cycle;  in fake_slave_set()
225 		dma_addr_t *buf_base, u32 *aspace, u32 *cycle)  in fake_slave_get()  argument
241 	*cycle = bridge->slaves[i].cycle;  in fake_slave_get()
253 		u32 aspace, u32 cycle, u32 dwidth)  in fake_master_set()  argument
321 	bridge->masters[i].cycle = cycle;  in fake_master_set()
340 		u32 *aspace, u32 *cycle, u32 *dwidth)  in __fake_master_get()  argument
353 	*cycle = bridge->masters[i].cycle;  in __fake_master_get()
362 		u32 *aspace, u32 *cycle, u32 *dwidth)  in fake_master_get()  argument
369 			cycle, dwidth);  in fake_master_get()
378 			  u32 aspace, u32 cycle)  in fake_lm_check()  argument
403 		if ((lm_aspace == aspace) && (lm_cycle == cycle)) {  in fake_lm_check()
419 					   u32 aspace, u32 cycle)  in fake_vmeread8()  argument
433 		if (cycle != bridge->slaves[i].cycle)  in fake_vmeread8()
445 	fake_lm_check(bridge, addr, aspace, cycle);  in fake_vmeread8()
452 					     u32 aspace, u32 cycle)  in fake_vmeread16()  argument
463 		if (cycle != bridge->slaves[i].cycle)  in fake_vmeread16()
478 	fake_lm_check(bridge, addr, aspace, cycle);  in fake_vmeread16()
485 					     u32 aspace, u32 cycle)  in fake_vmeread32()  argument
496 		if (cycle != bridge->slaves[i].cycle)  in fake_vmeread32()
511 	fake_lm_check(bridge, addr, aspace, cycle);  in fake_vmeread32()
520 	u32 aspace, cycle, dwidth;  in fake_master_read()  local
536 	cycle = priv->masters[i].cycle;  in fake_master_read()
550 		*(u8 *)buf = fake_vmeread8(priv, addr, aspace, cycle);  in fake_master_read()
559 						addr + done, aspace, cycle);  in fake_master_read()
564 						addr + done, aspace, cycle);  in fake_master_read()
574 					aspace, cycle);  in fake_master_read()
581 					aspace, cycle);  in fake_master_read()
588 					aspace, cycle);  in fake_master_read()
597 					aspace, cycle);  in fake_master_read()
603 				cycle);  in fake_master_read()
617 					      u32 aspace, u32 cycle)  in fake_vmewrite8()  argument
627 		if (cycle != bridge->slaves[i].cycle)  in fake_vmewrite8()
642 	fake_lm_check(bridge, addr, aspace, cycle);  in fake_vmewrite8()
648 					       u32 aspace, u32 cycle)  in fake_vmewrite16()  argument
658 		if (cycle != bridge->slaves[i].cycle)  in fake_vmewrite16()
673 	fake_lm_check(bridge, addr, aspace, cycle);  in fake_vmewrite16()
679 					       u32 aspace, u32 cycle)  in fake_vmewrite32()  argument
689 		if (cycle != bridge->slaves[i].cycle)  in fake_vmewrite32()
704 	fake_lm_check(bridge, addr, aspace, cycle);  in fake_vmewrite32()
712 	u32 aspace, cycle, dwidth;  in fake_master_write()  local
729 	cycle = bridge->masters[i].cycle;  in fake_master_write()
738 		fake_vmewrite8(bridge, (u8 *)buf, addr, aspace, cycle);  in fake_master_write()
748 						addr + done, aspace, cycle);  in fake_master_write()
753 						addr + done, aspace, cycle);  in fake_master_write()
763 					addr + done, aspace, cycle);  in fake_master_write()
770 					addr + done, aspace, cycle);  in fake_master_write()
777 					aspace, cycle);  in fake_master_write()
786 					addr + done, aspace, cycle);  in fake_master_write()
793 				cycle);  in fake_master_write()
815 	u32 aspace, cycle;  in fake_master_rmw()  local
826 	cycle = bridge->masters[i].cycle;  in fake_master_rmw()
832 	tmp = fake_vmeread32(bridge, base + offset, aspace, cycle);  in fake_master_rmw()
840 		fake_vmewrite32(bridge, &tmp, base + offset, aspace, cycle);  in fake_master_rmw()
857 		u32 aspace, u32 cycle)  in fake_lm_set()  argument
892 	bridge->lm_cycle = cycle;  in fake_lm_set()
903 		unsigned long long *lm_base, u32 *aspace, u32 *cycle)  in fake_lm_get()  argument
913 	*cycle = bridge->lm_cycle;  in fake_lm_get()