Lines Matching full:12
194 #define RT5651_BST_MASK1 (0xf<<12)
195 #define RT5651_BST_SFT1 12
233 #define RT5651_M_DAC_R2_VOL (0x1 << 12)
234 #define RT5651_M_DAC_R2_VOL_SFT 12
263 #define RT5651_ADC_R_BST_MASK (0x3 << 12)
264 #define RT5651_ADC_R_BST_SFT 12
273 #define RT5651_STO1_ADC_1_SRC_MASK (0x1 << 12)
274 #define RT5651_STO1_ADC_1_SRC_SFT 12
275 #define RT5651_STO1_ADC_1_SRC_ADC (0x1 << 12)
276 #define RT5651_STO1_ADC_1_SRC_DACMIX (0x0 << 12)
291 #define RT5651_STO2_ADC_L1_SRC_MASK (0x1 << 12)
292 #define RT5651_STO2_ADC_L1_SRC_SFT 12
293 #define RT5651_STO2_ADC_L1_SRC_DACMIXL (0x0 << 12)
294 #define RT5651_STO2_ADC_L1_SRC_ADCL (0x1 << 12)
327 #define RT5651_M_DAC_L2_MIXL (0x1 << 12)
328 #define RT5651_M_DAC_L2_MIXL_SFT 12
353 #define RT5651_M_STO_DD_L2 (0x1 << 12)
354 #define RT5651_M_STO_DD_L2_SFT 12
381 #define RT5651_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
382 #define RT5651_DAC_L2_DAC_L_VOL_SFT 12
409 #define RT5651_DAC_R2_SEL_MASK (0x3 << 12)
410 #define RT5651_DAC_R2_SEL_SFT 12
411 #define RT5651_DAC_R2_SEL_IF2 (0x0 << 12)
412 #define RT5651_DAC_R2_SEL_IF3 (0x1 << 12)
413 #define RT5651_DAC_R2_SEL_TXDC (0x2 << 12)
476 #define RT5651_M_PDM_R (0x1 << 12)
477 #define RT5651_M_PDM_R_SFT 12
493 #define RT5651_PDM_I2C_ID_MASK (0xf << 12)
568 #define RT5651_G_HPOMIX_MASK (0x1 << 12)
569 #define RT5651_G_HPOMIX_SFT 12
574 #define RT5651_G_IN_L_SM_L_MASK (0x3 << 12)
575 #define RT5651_G_IN_L_SM_L_SFT 12
596 #define RT5651_G_IN_R_SM_R_MASK (0x3 << 12)
597 #define RT5651_G_IN_R_SM_R_SFT 12
622 #define RT5651_M_SV_L_SPM_L (0x1 << 12)
623 #define RT5651_M_SV_L_SPM_L_SFT 12
630 #define RT5651_M_SV_R_SPM_R (0x1 << 12)
631 #define RT5651_M_SV_R_SPM_R_SFT 12
646 #define RT5651_M_OV_L_MM (0x1 << 12)
647 #define RT5651_M_OV_L_MM_SFT 12
720 #define RT5651_M_OV_R_LM (0x1 << 12)
721 #define RT5651_M_OV_R_LM_SFT 12
730 #define RT5651_PWR_DAC_L1 (0x1 << 12)
731 #define RT5651_PWR_DAC_L1_BIT 12
758 #define RT5651_PWR_LM (0x1 << 12)
759 #define RT5651_PWR_LM_BIT 12
817 #define RT5651_PWR_OV_R (0x1 << 12)
818 #define RT5651_PWR_OV_R_BIT 12
865 #define RT5651_I2S_PD1_MASK (0x7 << 12)
866 #define RT5651_I2S_PD1_SFT 12
867 #define RT5651_I2S_PD1_1 (0x0 << 12)
868 #define RT5651_I2S_PD1_2 (0x1 << 12)
869 #define RT5651_I2S_PD1_3 (0x2 << 12)
870 #define RT5651_I2S_PD1_4 (0x3 << 12)
871 #define RT5651_I2S_PD1_6 (0x4 << 12)
872 #define RT5651_I2S_PD1_8 (0x5 << 12)
873 #define RT5651_I2S_PD1_12 (0x6 << 12)
874 #define RT5651_I2S_PD1_16 (0x7 << 12)
917 #define RT5651_DMIC_1R_LH_MASK (0x1 << 12)
918 #define RT5651_DMIC_1R_LH_SFT 12
919 #define RT5651_DMIC_1R_LH_FALLING (0x0 << 12)
920 #define RT5651_DMIC_1R_LH_RISING (0x1 << 12)
938 #define RT5651_TDM_CH_NUM_SEL_MASK (0x3 << 12)
939 #define RT5651_TDM_CH_NUM_SEL_SFT 12
940 #define RT5651_TDM_CH_NUM_SEL_2 (0x0 << 12)
941 #define RT5651_TDM_CH_NUM_SEL_4 (0x1 << 12)
942 #define RT5651_TDM_CH_NUM_SEL_6 (0x2 << 12)
943 #define RT5651_TDM_CH_NUM_SEL_8 (0x3 << 12)
994 #define RT5651_TDM_LPBK_EN (0x1 << 12)
995 #define RT5651_TDM_LPBK_SFT 12
1020 #define RT5651_CH2_L_SEL_MASK (0x7 << 12)
1021 #define RT5651_CH2_L_SEL_SFT 12
1022 #define RT5651_CH2_L_SEL_SL0 (0x0 << 12)
1023 #define RT5651_CH2_L_SEL_SL1 (0x1 << 12)
1024 #define RT5651_CH2_L_SEL_SL2 (0x2 << 12)
1025 #define RT5651_CH2_L_SEL_SL3 (0x3 << 12)
1026 #define RT5651_CH2_L_SEL_SL4 (0x4 << 12)
1027 #define RT5651_CH2_L_SEL_SL5 (0x5 << 12)
1028 #define RT5651_CH2_L_SEL_SL6 (0x6 << 12)
1029 #define RT5651_CH2_L_SEL_SL7 (0x7 << 12)
1067 #define RT5651_PLL1_SRC_MASK (0x3 << 12)
1068 #define RT5651_PLL1_SRC_SFT 12
1069 #define RT5651_PLL1_SRC_MCLK (0x0 << 12)
1070 #define RT5651_PLL1_SRC_BCLK1 (0x1 << 12)
1071 #define RT5651_PLL1_SRC_BCLK2 (0x2 << 12)
1089 #define RT5651_PLL_M_MASK (RT5651_PLL_M_MAX << 12)
1090 #define RT5651_PLL_M_SFT 12
1099 #define RT5651_STO2_T_MASK (0x1 << 12)
1100 #define RT5651_STO2_T_SFT 12
1101 #define RT5651_STO2_T_I2S2 (0x0 << 12)
1102 #define RT5651_STO2_T_LRCK2 (0x1 << 12)
1121 #define RT5651_STO2_DAC_M_MASK (0x1 << 12)
1122 #define RT5651_STO2_DAC_M_SFT 12
1123 #define RT5651_STO2_DAC_M_NOR (0x0 << 12)
1124 #define RT5651_STO2_DAC_M_ASRC (0x1 << 12)
1144 #define RT5651_I2S1_RATE_MASK (0xf << 12)
1145 #define RT5651_I2S1_RATE_SFT 12
1162 #define RT5651_I2S1_PD_MASK (0x7 << 12)
1163 #define RT5651_I2S1_PD_SFT 12
1168 #define RT5651_FSI1_RATE_MASK (0xf << 12)
1169 #define RT5651_FSI1_RATE_SFT 12
1236 #define RT5651_RAMP_MASK (0x1 << 12)
1237 #define RT5651_RAMP_SFT 12
1238 #define RT5651_RAMP_DIS (0x0 << 12)
1239 #define RT5651_RAMP_EN (0x1 << 12)
1266 #define RT5651_CP_SYS_MASK (0x7 << 12)
1267 #define RT5651_CP_SYS_SFT 12
1332 #define RT5651_JD2_CMP_MASK (0x7 << 12)
1333 #define RT5651_JD2_CMP_SFT 12
1356 #define RT5651_JD3_CMP_MASK (0x7 << 12)
1357 #define RT5651_JD3_CMP_SFT 12
1479 #define RT5651_ALC_NGB_MASK (0xf << 12)
1480 #define RT5651_ALC_NGB_SFT 12
1610 #define RT5651_STA_JD1_1 (0x1 << 12)
1611 #define RT5651_STA_JD1_1_BIT 12
1676 #define RT5651_GP5_P_MASK (0x1 << 12)
1677 #define RT5651_GP5_P_SFT 12
1678 #define RT5651_GP5_P_NOR (0x0 << 12)
1679 #define RT5651_GP5_P_INV (0x1 << 12)
1782 #define RT5651_BB_CT_MASK (0x7 << 12)
1783 #define RT5651_BB_CT_SFT 12
1784 #define RT5651_BB_CT_A (0x0 << 12)
1785 #define RT5651_BB_CT_B (0x1 << 12)
1786 #define RT5651_BB_CT_C (0x2 << 12)
1787 #define RT5651_BB_CT_D (0x3 << 12)
1862 #define RT5651_HPF_CF_L_MASK (0x7 << 12)
1863 #define RT5651_HPF_CF_L_SFT 12
1927 #define RT5651_HP_SV_MASK (0x1 << 12)
1928 #define RT5651_HP_SV_SFT 12
1929 #define RT5651_HP_SV_DIS (0x0 << 12)
1930 #define RT5651_HP_SV_EN (0x1 << 12)
2017 #define RT5651_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2018 #define RT5651_WND_STRONG_SFT 12