Lines Matching refs:iview
6506 radv_surface_max_layer_count(struct radv_image_view *iview) in radv_surface_max_layer_count() argument
6508 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth in radv_surface_max_layer_count()
6509 : (iview->base_layer + iview->layer_count); in radv_surface_max_layer_count()
6514 const struct radv_image_view *iview) in get_dcc_max_uncompressed_block_size() argument
6516 if (device->physical_device->rad_info.chip_class < GFX10 && iview->image->info.samples > 1) { in get_dcc_max_uncompressed_block_size()
6517 if (iview->image->planes[0].surface.bpe == 1) in get_dcc_max_uncompressed_block_size()
6519 else if (iview->image->planes[0].surface.bpe == 2) in get_dcc_max_uncompressed_block_size()
6542 radv_init_dcc_control_reg(struct radv_device *device, struct radv_image_view *iview) in radv_init_dcc_control_reg() argument
6544 unsigned max_uncompressed_block_size = get_dcc_max_uncompressed_block_size(device, iview); in radv_init_dcc_control_reg()
6550 if (!radv_dcc_enabled(iview->image, iview->base_mip)) in radv_init_dcc_control_reg()
6557 iview->image->planes[0].surface.u.gfx9.color.dcc.max_compressed_block_size; in radv_init_dcc_control_reg()
6558 …independent_128b_blocks = iview->image->planes[0].surface.u.gfx9.color.dcc.independent_128B_blocks; in radv_init_dcc_control_reg()
6559 … independent_64b_blocks = iview->image->planes[0].surface.u.gfx9.color.dcc.independent_64B_blocks; in radv_init_dcc_control_reg()
6563 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_TRANSFER_SRC_BIT | in radv_init_dcc_control_reg()
6589 struct radv_image_view *iview) in radv_initialise_color_surface() argument
6595 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id]; in radv_initialise_color_surface()
6598 desc = vk_format_description(iview->vk_format); in radv_initialise_color_surface()
6605 va = radv_buffer_get_va(iview->image->bo) + iview->image->offset; in radv_initialise_color_surface()
6634 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip]; in radv_initialise_color_surface()
6643 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false); in radv_initialise_color_surface()
6651 if (radv_image_has_fmask(iview->image)) { in radv_initialise_color_surface()
6667 va = radv_buffer_get_va(iview->image->bo) + iview->image->offset; in radv_initialise_color_surface()
6671 va = radv_buffer_get_va(iview->image->bo) + iview->image->offset; in radv_initialise_color_surface()
6674 if (radv_dcc_enabled(iview->image, iview->base_mip) && in radv_initialise_color_surface()
6676 va += plane->surface.u.legacy.color.dcc_level[iview->base_mip].dcc_offset; in radv_initialise_color_surface()
6685 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1; in radv_initialise_color_surface()
6687 S_028C6C_SLICE_START(iview->base_layer) | S_028C6C_SLICE_MAX_GFX10(max_slice); in radv_initialise_color_surface()
6689 if (iview->image->info.samples > 1) { in radv_initialise_color_surface()
6690 unsigned log_samples = util_logbase2(iview->image->info.samples); in radv_initialise_color_surface()
6696 if (radv_image_has_fmask(iview->image)) { in radv_initialise_color_surface()
6697 va = radv_buffer_get_va(iview->image->bo) + iview->image->offset + surf->fmask_offset; in radv_initialise_color_surface()
6704 ntype = radv_translate_color_numformat(iview->vk_format, desc, in radv_initialise_color_surface()
6705 vk_format_get_first_non_void_channel(iview->vk_format)); in radv_initialise_color_surface()
6706 format = radv_translate_colorformat(iview->vk_format); in radv_initialise_color_surface()
6709 swap = radv_translate_colorswap(iview->vk_format, false); in radv_initialise_color_surface()
6739 if (radv_image_has_fmask(iview->image)) { in radv_initialise_color_surface()
6746 if (radv_image_is_tc_compat_cmask(iview->image)) { in radv_initialise_color_surface()
6763 if (radv_image_has_cmask(iview->image) && in radv_initialise_color_surface()
6767 if (radv_dcc_enabled(iview->image, iview->base_mip)) in radv_initialise_color_surface()
6770 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview); in radv_initialise_color_surface()
6773 if (!radv_image_has_fmask(iview->image) && in radv_initialise_color_surface()
6780 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D in radv_initialise_color_surface()
6781 ? (iview->extent.depth - 1) in radv_initialise_color_surface()
6782 : (iview->image->info.array_size - 1); in radv_initialise_color_surface()
6784 vk_format_get_plane_width(iview->image->vk_format, iview->plane_id, iview->extent.width); in radv_initialise_color_surface()
6786 vk_format_get_plane_height(iview->image->vk_format, iview->plane_id, iview->extent.height); in radv_initialise_color_surface()
6789 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip); in radv_initialise_color_surface()
6795 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip); in radv_initialise_color_surface()
6801 S_028C68_MAX_MIP(iview->image->info.levels - 1); in radv_initialise_color_surface()
6806 radv_calc_decompress_on_z_planes(struct radv_device *device, struct radv_image_view *iview) in radv_calc_decompress_on_z_planes() argument
6810 assert(radv_image_is_tc_compat_htile(iview->image)); in radv_calc_decompress_on_z_planes()
6816 if (iview->vk_format == VK_FORMAT_D16_UNORM && iview->image->info.samples > 1) in radv_calc_decompress_on_z_planes()
6821 radv_image_get_iterate256(device, iview->image) && in radv_calc_decompress_on_z_planes()
6822 !radv_image_tile_stencil_disabled(device, iview->image) && in radv_calc_decompress_on_z_planes()
6823 iview->image->info.samples == 4) { in radv_calc_decompress_on_z_planes()
6829 if (iview->vk_format == VK_FORMAT_D16_UNORM) { in radv_calc_decompress_on_z_planes()
6838 if (iview->image->info.samples <= 1) in radv_calc_decompress_on_z_planes()
6840 else if (iview->image->info.samples <= 4) in radv_calc_decompress_on_z_planes()
6877 struct radv_image_view *iview) in radv_initialise_ds_surface() argument
6879 unsigned level = iview->base_mip; in radv_initialise_ds_surface()
6882 bool stencil_only = iview->image->vk_format == VK_FORMAT_S8_UINT; in radv_initialise_ds_surface()
6883 const struct radv_image_plane *plane = &iview->image->planes[0]; in radv_initialise_ds_surface()
6886 assert(vk_format_get_plane_count(iview->image->vk_format) == 1); in radv_initialise_ds_surface()
6890 switch (iview->image->vk_format) { in radv_initialise_ds_surface()
6909 format = radv_translate_dbformat(iview->image->vk_format); in radv_initialise_ds_surface()
6912 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1; in radv_initialise_ds_surface()
6913 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) | S_028008_SLICE_MAX(max_slice); in radv_initialise_ds_surface()
6916 S_028008_SLICE_START_HI(iview->base_layer >> 11) | S_028008_SLICE_MAX_HI(max_slice >> 11); in radv_initialise_ds_surface()
6922 va = radv_buffer_get_va(iview->image->bo) + iview->image->offset; in radv_initialise_ds_surface()
6930 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) | in radv_initialise_ds_surface()
6932 S_028038_MAXMIP(iview->image->info.levels - 1) | S_028038_ZRANGE_PRECISION(1); in radv_initialise_ds_surface()
6942 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) | in radv_initialise_ds_surface()
6943 S_02801C_Y_MAX(iview->image->info.height - 1); in radv_initialise_ds_surface()
6945 if (radv_htile_enabled(iview->image, level)) { in radv_initialise_ds_surface()
6948 if (radv_image_is_tc_compat_htile(iview->image)) { in radv_initialise_ds_surface()
6949 unsigned max_zplanes = radv_calc_decompress_on_z_planes(device, iview); in radv_initialise_ds_surface()
6954 bool iterate256 = radv_image_get_iterate256(device, iview->image); in radv_initialise_ds_surface()
6966 if (radv_image_tile_stencil_disabled(device, iview->image)) { in radv_initialise_ds_surface()
6970 va = radv_buffer_get_va(iview->image->bo) + iview->image->offset + surf->meta_offset; in radv_initialise_ds_surface()
6978 if (radv_image_has_vrs_htile(device, iview->image)) { in radv_initialise_ds_surface()
6991 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image)); in radv_initialise_ds_surface()
6995 if (iview->image->info.samples > 1) in radv_initialise_ds_surface()
6996 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples)); in radv_initialise_ds_surface()
7019 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false); in radv_initialise_ds_surface()
7021 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true); in radv_initialise_ds_surface()
7032 if (radv_htile_enabled(iview->image, level)) { in radv_initialise_ds_surface()
7035 if (radv_image_tile_stencil_disabled(device, iview->image)) { in radv_initialise_ds_surface()
7039 va = radv_buffer_get_va(iview->image->bo) + iview->image->offset + surf->meta_offset; in radv_initialise_ds_surface()
7043 if (radv_image_is_tc_compat_htile(iview->image)) { in radv_initialise_ds_surface()
7044 unsigned max_zplanes = radv_calc_decompress_on_z_planes(device, iview); in radv_initialise_ds_surface()
7086 struct radv_image_view *iview = radv_image_view_from_handle(_iview); in radv_CreateFramebuffer() local
7087 framebuffer->attachments[i] = iview; in radv_CreateFramebuffer()