Lines Matching refs:alu
567 inst->alu.add.op == V3D_QPU_A_TMUWT)); in v3d_qpu_waits_on_tmu()
646 if (inst->alu.add.magic_write && in v3d_qpu_uses_tlb()
647 v3d_qpu_magic_waddr_is_tlb(inst->alu.add.waddr)) { in v3d_qpu_uses_tlb()
651 if (inst->alu.mul.magic_write && in v3d_qpu_uses_tlb()
652 v3d_qpu_magic_waddr_is_tlb(inst->alu.mul.waddr)) { in v3d_qpu_uses_tlb()
667 if (inst->alu.add.magic_write && in v3d_qpu_uses_sfu()
668 v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr)) { in v3d_qpu_uses_sfu()
672 if (inst->alu.mul.magic_write && in v3d_qpu_uses_sfu()
673 v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr)) { in v3d_qpu_uses_sfu()
685 switch (inst->alu.add.op) { in v3d_qpu_instr_is_sfu()
705 ((inst->alu.add.magic_write && in v3d_qpu_writes_tmu()
706 v3d_qpu_magic_waddr_is_tmu(devinfo, inst->alu.add.waddr)) || in v3d_qpu_writes_tmu()
707 (inst->alu.mul.magic_write && in v3d_qpu_writes_tmu()
708 v3d_qpu_magic_waddr_is_tmu(devinfo, inst->alu.mul.waddr)))); in v3d_qpu_writes_tmu()
716 (!inst->alu.add.magic_write || in v3d_qpu_writes_tmu_not_tmuc()
717 inst->alu.add.waddr != V3D_QPU_WADDR_TMUC) && in v3d_qpu_writes_tmu_not_tmuc()
718 (!inst->alu.mul.magic_write || in v3d_qpu_writes_tmu_not_tmuc()
719 inst->alu.mul.waddr != V3D_QPU_WADDR_TMUC); in v3d_qpu_writes_tmu_not_tmuc()
729 if (v3d_qpu_add_op_reads_vpm(inst->alu.add.op)) in v3d_qpu_reads_vpm()
740 if (v3d_qpu_add_op_writes_vpm(inst->alu.add.op)) in v3d_qpu_writes_vpm()
743 if (inst->alu.add.magic_write && in v3d_qpu_writes_vpm()
744 v3d_qpu_magic_waddr_is_vpm(inst->alu.add.waddr)) { in v3d_qpu_writes_vpm()
748 if (inst->alu.mul.magic_write && in v3d_qpu_writes_vpm()
749 v3d_qpu_magic_waddr_is_vpm(inst->alu.mul.waddr)) { in v3d_qpu_writes_vpm()
765 if (inst->alu.add.op != V3D_QPU_A_NOP && in v3d_qpu_writes_unifa()
766 inst->alu.add.magic_write && in v3d_qpu_writes_unifa()
767 inst->alu.add.waddr == V3D_QPU_WADDR_UNIFA) { in v3d_qpu_writes_unifa()
771 if (inst->alu.mul.op != V3D_QPU_M_NOP && in v3d_qpu_writes_unifa()
772 inst->alu.mul.magic_write && in v3d_qpu_writes_unifa()
773 inst->alu.mul.waddr == V3D_QPU_WADDR_UNIFA) { in v3d_qpu_writes_unifa()
785 inst->alu.add.op == V3D_QPU_A_VPMWT; in v3d_qpu_waits_vpm()
808 if (inst->alu.add.magic_write && inst->alu.add.waddr == waddr) in qpu_writes_magic_waddr_explicitly()
811 if (inst->alu.mul.magic_write && inst->alu.mul.waddr == waddr) in qpu_writes_magic_waddr_explicitly()
838 if (inst->alu.add.magic_write && in v3d_qpu_writes_r4()
839 (inst->alu.add.waddr == V3D_QPU_WADDR_R4 || in v3d_qpu_writes_r4()
840 v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr))) { in v3d_qpu_writes_r4()
844 if (inst->alu.mul.magic_write && in v3d_qpu_writes_r4()
845 (inst->alu.mul.waddr == V3D_QPU_WADDR_R4 || in v3d_qpu_writes_r4()
846 v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr))) { in v3d_qpu_writes_r4()
894 int add_nsrc = v3d_qpu_add_op_num_src(inst->alu.add.op); in v3d_qpu_uses_mux()
895 int mul_nsrc = v3d_qpu_mul_op_num_src(inst->alu.mul.op); in v3d_qpu_uses_mux()
897 return ((add_nsrc > 0 && inst->alu.add.a == mux) || in v3d_qpu_uses_mux()
898 (add_nsrc > 1 && inst->alu.add.b == mux) || in v3d_qpu_uses_mux()
899 (mul_nsrc > 0 && inst->alu.mul.a == mux) || in v3d_qpu_uses_mux()
900 (mul_nsrc > 1 && inst->alu.mul.b == mux)); in v3d_qpu_uses_mux()
930 switch (inst->alu.add.op) { in v3d_qpu_reads_flags()
967 switch (inst->alu.add.op) { in v3d_qpu_unpacks_f32()
991 switch (inst->alu.mul.op) { in v3d_qpu_unpacks_f32()
1008 switch (inst->alu.add.op) { in v3d_qpu_unpacks_f16()
1017 switch (inst->alu.mul.op) { in v3d_qpu_unpacks_f16()
1035 if (inst->alu.add.op != V3D_QPU_A_NOP) in v3d_qpu_is_nop()
1037 if (inst->alu.mul.op != V3D_QPU_M_NOP) in v3d_qpu_is_nop()