Lines Matching refs:cs
42 struct tu_cs *cs, in tu6_emit_event_write() argument
59 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1); in tu6_emit_event_write()
60 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event)); in tu6_emit_event_write()
62 tu_cs_emit_qw(cs, global_iova(cmd, seqno_dummy)); in tu6_emit_event_write()
63 tu_cs_emit(cs, 0); in tu6_emit_event_write()
69 struct tu_cs *cs, in tu6_emit_flushes() argument
87 tu6_emit_event_write(cmd_buffer, cs, PC_CCU_FLUSH_COLOR_TS); in tu6_emit_flushes()
90 tu6_emit_event_write(cmd_buffer, cs, PC_CCU_FLUSH_DEPTH_TS); in tu6_emit_flushes()
92 tu6_emit_event_write(cmd_buffer, cs, PC_CCU_INVALIDATE_COLOR); in tu6_emit_flushes()
94 tu6_emit_event_write(cmd_buffer, cs, PC_CCU_INVALIDATE_DEPTH); in tu6_emit_flushes()
96 tu6_emit_event_write(cmd_buffer, cs, CACHE_FLUSH_TS); in tu6_emit_flushes()
98 tu6_emit_event_write(cmd_buffer, cs, CACHE_INVALIDATE); in tu6_emit_flushes()
100 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0); in tu6_emit_flushes()
104 tu_cs_emit_wfi(cs); in tu6_emit_flushes()
106 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0); in tu6_emit_flushes()
113 struct tu_cs *cs) in tu_emit_cache_flush() argument
115 tu6_emit_flushes(cmd_buffer, cs, cmd_buffer->state.cache.flush_bits); in tu_emit_cache_flush()
123 struct tu_cs *cs) in tu_emit_cache_flush_renderpass() argument
128 tu6_emit_flushes(cmd_buffer, cs, cmd_buffer->state.renderpass_cache.flush_bits); in tu_emit_cache_flush_renderpass()
139 struct tu_cs *cs, in tu_emit_cache_flush_ccu() argument
170 tu6_emit_flushes(cmd_buffer, cs, flushes); in tu_emit_cache_flush_ccu()
175 tu_cs_emit_regs(cs, in tu_emit_cache_flush_ccu()
188 struct tu_cs *cs) in tu6_emit_zs() argument
192 tu_cs_emit_regs(cs, in tu6_emit_zs()
199 tu_cs_emit_regs(cs, in tu6_emit_zs()
202 tu_cs_emit_regs(cs, in tu6_emit_zs()
207 tu_cs_emit_regs(cs, A6XX_RB_STENCIL_INFO(0)); in tu6_emit_zs()
217 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6); in tu6_emit_zs()
218 tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt).value); in tu6_emit_zs()
219 tu_cs_image_ref(cs, iview, 0); in tu6_emit_zs()
220 tu_cs_emit(cs, attachment->gmem_offset); in tu6_emit_zs()
222 tu_cs_emit_regs(cs, in tu6_emit_zs()
225 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE, 3); in tu6_emit_zs()
226 tu_cs_image_flag_ref(cs, iview, 0); in tu6_emit_zs()
228 tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_BUFFER_BASE(.bo = iview->image->bo, in tu6_emit_zs()
236 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 6); in tu6_emit_zs()
237 tu_cs_emit(cs, A6XX_RB_STENCIL_INFO(.separate_stencil = true).value); in tu6_emit_zs()
239 tu_cs_image_stencil_ref(cs, iview, 0); in tu6_emit_zs()
240 tu_cs_emit(cs, attachment->gmem_offset_stencil); in tu6_emit_zs()
242 tu_cs_image_ref(cs, iview, 0); in tu6_emit_zs()
243 tu_cs_emit(cs, attachment->gmem_offset); in tu6_emit_zs()
246 tu_cs_emit_regs(cs, in tu6_emit_zs()
254 struct tu_cs *cs) in tu6_emit_mrt() argument
265 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6); in tu6_emit_mrt()
266 tu_cs_emit(cs, iview->RB_MRT_BUF_INFO); in tu6_emit_mrt()
267 tu_cs_image_ref(cs, iview, 0); in tu6_emit_mrt()
268 tu_cs_emit(cs, cmd->state.pass->attachments[a].gmem_offset); in tu6_emit_mrt()
270 tu_cs_emit_regs(cs, in tu6_emit_mrt()
273 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(i), 3); in tu6_emit_mrt()
274 tu_cs_image_flag_ref(cs, iview, 0); in tu6_emit_mrt()
277 tu_cs_emit_regs(cs, in tu6_emit_mrt()
279 tu_cs_emit_regs(cs, in tu6_emit_mrt()
283 tu_cs_emit_regs(cs, A6XX_GRAS_MAX_LAYER_INDEX(layers - 1)); in tu6_emit_mrt()
285 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SC_CNTL, in tu6_emit_mrt()
297 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM); in tu6_emit_mrt()
298 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SC_CNTL, in tu6_emit_mrt()
302 tu_cond_exec_end(cs); in tu6_emit_mrt()
307 tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits vk_samples, in tu6_emit_msaa() argument
313 tu_cs_emit_regs(cs, in tu6_emit_msaa()
318 tu_cs_emit_regs(cs, in tu6_emit_msaa()
323 tu_cs_emit_regs(cs, in tu6_emit_msaa()
328 tu_cs_emit_regs(cs, in tu6_emit_msaa()
333 tu6_emit_bin_size(struct tu_cs *cs, in tu6_emit_bin_size() argument
336 tu_cs_emit_regs(cs, in tu6_emit_bin_size()
341 tu_cs_emit_regs(cs, in tu6_emit_bin_size()
347 tu_cs_emit_regs(cs, in tu6_emit_bin_size()
355 struct tu_cs *cs, in tu6_emit_render_cntl() argument
388 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CNTL, 1); in tu6_emit_render_cntl()
389 tu_cs_emit(cs, cntl); in tu6_emit_render_cntl()
398 tu_cs_reserve(cs, 3 + 4); in tu6_emit_render_cntl()
399 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2); in tu6_emit_render_cntl()
400 tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) | in tu6_emit_render_cntl()
402 tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(4)); in tu6_emit_render_cntl()
405 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3); in tu6_emit_render_cntl()
406 tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL)); in tu6_emit_render_cntl()
407 tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL); in tu6_emit_render_cntl()
408 tu_cs_emit(cs, cntl); in tu6_emit_render_cntl()
412 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align) in tu6_emit_blit_scissor() argument
439 tu_cs_emit_regs(cs, in tu6_emit_blit_scissor()
445 tu6_emit_window_scissor(struct tu_cs *cs, in tu6_emit_window_scissor() argument
451 tu_cs_emit_regs(cs, in tu6_emit_window_scissor()
455 tu_cs_emit_regs(cs, in tu6_emit_window_scissor()
461 tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1) in tu6_emit_window_offset() argument
463 tu_cs_emit_regs(cs, in tu6_emit_window_offset()
466 tu_cs_emit_regs(cs, in tu6_emit_window_offset()
469 tu_cs_emit_regs(cs, in tu6_emit_window_offset()
472 tu_cs_emit_regs(cs, in tu6_emit_window_offset()
495 tu_cs_emit_draw_state(struct tu_cs *cs, uint32_t id, struct tu_draw_state state) in tu_cs_emit_draw_state() argument
543 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(state.size) | in tu_cs_emit_draw_state()
547 tu_cs_emit_qw(cs, state.iova); in tu_cs_emit_draw_state()
600 struct tu_cs *cs, in tu6_emit_tile_select() argument
605 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1); in tu6_emit_tile_select()
606 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM)); in tu6_emit_tile_select()
612 tu6_emit_window_scissor(cs, x1, y1, x2, y2); in tu6_emit_tile_select()
613 tu6_emit_window_offset(cs, x1, y1); in tu6_emit_tile_select()
615 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false)); in tu6_emit_tile_select()
618 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0); in tu6_emit_tile_select()
620 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1); in tu6_emit_tile_select()
621 tu_cs_emit(cs, 0x0); in tu6_emit_tile_select()
623 tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5_OFFSET, 4); in tu6_emit_tile_select()
624 tu_cs_emit(cs, fb->pipe_sizes[pipe] | in tu6_emit_tile_select()
626 tu_cs_emit(cs, pipe * cmd->vsc_draw_strm_pitch); in tu6_emit_tile_select()
627 tu_cs_emit(cs, pipe * 4); in tu6_emit_tile_select()
628 tu_cs_emit(cs, pipe * cmd->vsc_prim_strm_pitch); in tu6_emit_tile_select()
630 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1); in tu6_emit_tile_select()
631 tu_cs_emit(cs, 0x0); in tu6_emit_tile_select()
633 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1); in tu6_emit_tile_select()
634 tu_cs_emit(cs, 0x0); in tu6_emit_tile_select()
636 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1); in tu6_emit_tile_select()
637 tu_cs_emit(cs, 0x1); in tu6_emit_tile_select()
639 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1); in tu6_emit_tile_select()
640 tu_cs_emit(cs, 0x0); in tu6_emit_tile_select()
646 struct tu_cs *cs, in tu6_emit_sysmem_resolve() argument
655 tu_resolve_sysmem(cmd, cs, src, dst, layer_mask, fb->layers, &cmd->state.render_area); in tu6_emit_sysmem_resolve()
660 struct tu_cs *cs, in tu6_emit_sysmem_resolves() argument
685 tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS); in tu6_emit_sysmem_resolves()
687 tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS); in tu6_emit_sysmem_resolves()
689 tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE); in tu6_emit_sysmem_resolves()
692 tu_cs_emit_wfi(cs); in tu6_emit_sysmem_resolves()
701 tu6_emit_sysmem_resolve(cmd, cs, subpass->multiview_mask, a, gmem_a); in tu6_emit_sysmem_resolves()
707 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs) in tu6_emit_tile_store() argument
712 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1); in tu6_emit_tile_store()
713 tu_cs_emit(cs, 0x0); in tu6_emit_tile_store()
715 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1); in tu6_emit_tile_store()
716 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE)); in tu6_emit_tile_store()
718 tu6_emit_blit_scissor(cmd, cs, true); in tu6_emit_tile_store()
722 tu_store_gmem_attachment(cmd, cs, a, a); in tu6_emit_tile_store()
730 tu_store_gmem_attachment(cmd, cs, a, gmem_a); in tu6_emit_tile_store()
737 tu_disable_draw_states(struct tu_cmd_buffer *cmd, struct tu_cs *cs) in tu_disable_draw_states() argument
739 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3); in tu_disable_draw_states()
740 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) | in tu_disable_draw_states()
743 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0)); in tu_disable_draw_states()
744 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0)); in tu_disable_draw_states()
750 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs) in tu6_init_hw() argument
755 tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE); in tu6_init_hw()
757 tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD( in tu6_init_hw()
771 tu_cs_emit_wfi(cs); in tu6_init_hw()
776 tu_cs_emit_regs(cs, in tu6_init_hw()
779 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000); in tu6_init_hw()
780 tu_cs_emit_write_reg(cs, REG_A6XX_SP_FLOAT_CNTL, 0); in tu6_init_hw()
781 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0); in tu6_init_hw()
782 tu_cs_emit_write_reg(cs, REG_A6XX_SP_PERFCTR_ENABLE, 0x3f); in tu6_init_hw()
783 tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_UNKNOWN_B605, 0x44); in tu6_init_hw()
784 tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_DBG_ECO_CNTL, in tu6_init_hw()
786 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80); in tu6_init_hw()
787 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0); in tu6_init_hw()
789 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0); in tu6_init_hw()
790 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_DBG_ECO_CNTL, 0x880); in tu6_init_hw()
791 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0); in tu6_init_hw()
792 tu_cs_emit_write_reg(cs, REG_A6XX_SP_CHICKEN_BITS, 0x00000410); in tu6_init_hw()
793 tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0); in tu6_init_hw()
794 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0); in tu6_init_hw()
795 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_SHARED_CONSTS, 0); in tu6_init_hw()
796 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000); in tu6_init_hw()
797 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4); in tu6_init_hw()
798 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0); in tu6_init_hw()
799 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A9A8, 0); in tu6_init_hw()
800 tu_cs_emit_write_reg(cs, REG_A6XX_SP_MODE_CONTROL, in tu6_init_hw()
804 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX); in tu6_init_hw()
805 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010); in tu6_init_hw()
806 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f); in tu6_init_hw()
808 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0); in tu6_init_hw()
810 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0); in tu6_init_hw()
811 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0); in tu6_init_hw()
812 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0); in tu6_init_hw()
813 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0); in tu6_init_hw()
814 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0); in tu6_init_hw()
815 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0); in tu6_init_hw()
816 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0); in tu6_init_hw()
817 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0); in tu6_init_hw()
819 tu_cs_emit_regs(cs, A6XX_VPC_POINT_COORD_INVERT(false)); in tu6_init_hw()
820 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0); in tu6_init_hw()
822 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true)); in tu6_init_hw()
824 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0); in tu6_init_hw()
826 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 0); in tu6_init_hw()
827 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0); in tu6_init_hw()
828 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0); in tu6_init_hw()
829 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0); in tu6_init_hw()
830 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0); in tu6_init_hw()
831 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0); in tu6_init_hw()
832 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_MODE_CNTL, in tu6_init_hw()
835 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc); in tu6_init_hw()
837 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000); in tu6_init_hw()
839 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x0000001f); in tu6_init_hw()
841 tu_cs_emit_regs(cs, A6XX_RB_ALPHA_CONTROL()); /* always disable alpha test */ in tu6_init_hw()
842 tu_cs_emit_regs(cs, A6XX_RB_DITHER_CNTL()); /* always disable dithering */ in tu6_init_hw()
844 tu_disable_draw_states(cmd, cs); in tu6_init_hw()
846 tu_cs_emit_regs(cs, in tu6_init_hw()
849 tu_cs_emit_regs(cs, in tu6_init_hw()
884 tu_cs_emit_regs(cs, in tu6_init_hw()
886 tu_cs_emit_regs(cs, in tu6_init_hw()
888 tu_cs_emit_regs(cs, in tu6_init_hw()
892 tu_cs_sanity_check(cs); in tu6_init_hw()
896 update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs) in update_vsc_pipe() argument
900 tu_cs_emit_regs(cs, in update_vsc_pipe()
904 tu_cs_emit_regs(cs, in update_vsc_pipe()
908 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32); in update_vsc_pipe()
909 tu_cs_emit_array(cs, fb->pipe_config, 32); in update_vsc_pipe()
911 tu_cs_emit_regs(cs, in update_vsc_pipe()
915 tu_cs_emit_regs(cs, in update_vsc_pipe()
921 emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs) in emit_vsc_overflow_test() argument
928 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8); in emit_vsc_overflow_test()
929 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) | in emit_vsc_overflow_test()
931 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i))); in emit_vsc_overflow_test()
932 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0)); in emit_vsc_overflow_test()
933 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_draw_strm_pitch - VSC_PAD)); in emit_vsc_overflow_test()
934 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0)); in emit_vsc_overflow_test()
935 tu_cs_emit_qw(cs, global_iova(cmd, vsc_draw_overflow)); in emit_vsc_overflow_test()
936 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(cmd->vsc_draw_strm_pitch)); in emit_vsc_overflow_test()
938 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8); in emit_vsc_overflow_test()
939 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) | in emit_vsc_overflow_test()
941 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i))); in emit_vsc_overflow_test()
942 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0)); in emit_vsc_overflow_test()
943 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_prim_strm_pitch - VSC_PAD)); in emit_vsc_overflow_test()
944 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0)); in emit_vsc_overflow_test()
945 tu_cs_emit_qw(cs, global_iova(cmd, vsc_prim_overflow)); in emit_vsc_overflow_test()
946 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(cmd->vsc_prim_strm_pitch)); in emit_vsc_overflow_test()
949 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0); in emit_vsc_overflow_test()
953 tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs) in tu6_emit_binning_pass() argument
958 tu6_emit_window_scissor(cs, 0, 0, fb->width - 1, fb->height - 1); in tu6_emit_binning_pass()
960 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1); in tu6_emit_binning_pass()
961 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING)); in tu6_emit_binning_pass()
963 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1); in tu6_emit_binning_pass()
964 tu_cs_emit(cs, 0x1); in tu6_emit_binning_pass()
966 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1); in tu6_emit_binning_pass()
967 tu_cs_emit(cs, 0x1); in tu6_emit_binning_pass()
969 tu_cs_emit_wfi(cs); in tu6_emit_binning_pass()
971 tu_cs_emit_regs(cs, in tu6_emit_binning_pass()
974 update_vsc_pipe(cmd, cs); in tu6_emit_binning_pass()
976 tu_cs_emit_regs(cs, in tu6_emit_binning_pass()
979 tu_cs_emit_regs(cs, in tu6_emit_binning_pass()
982 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1); in tu6_emit_binning_pass()
983 tu_cs_emit(cs, UNK_2C); in tu6_emit_binning_pass()
985 tu_cs_emit_regs(cs, in tu6_emit_binning_pass()
988 tu_cs_emit_regs(cs, in tu6_emit_binning_pass()
991 trace_start_binning_ib(&cmd->trace, cs); in tu6_emit_binning_pass()
994 tu_cs_emit_call(cs, &cmd->draw_cs); in tu6_emit_binning_pass()
996 trace_end_binning_ib(&cmd->trace, cs); in tu6_emit_binning_pass()
1005 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3); in tu6_emit_binning_pass()
1006 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) | in tu6_emit_binning_pass()
1009 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0)); in tu6_emit_binning_pass()
1010 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0)); in tu6_emit_binning_pass()
1012 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1); in tu6_emit_binning_pass()
1013 tu_cs_emit(cs, UNK_2D); in tu6_emit_binning_pass()
1023 tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS); in tu6_emit_binning_pass()
1025 tu_cs_emit_wfi(cs); in tu6_emit_binning_pass()
1027 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0); in tu6_emit_binning_pass()
1029 emit_vsc_overflow_test(cmd, cs); in tu6_emit_binning_pass()
1031 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1); in tu6_emit_binning_pass()
1032 tu_cs_emit(cs, 0x0); in tu6_emit_binning_pass()
1034 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1); in tu6_emit_binning_pass()
1035 tu_cs_emit(cs, 0x0); in tu6_emit_binning_pass()
1129 struct tu_cs cs; in tu_emit_input_attachments() local
1130 struct tu_draw_state ds = tu_cs_draw_state(&cmd->sub_cs, &cs, 9); in tu_emit_input_attachments()
1132 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_FRAG, 3); in tu_emit_input_attachments()
1133 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) | in tu_emit_input_attachments()
1138 tu_cs_emit_qw(&cs, texture.iova); in tu_emit_input_attachments()
1140 tu_cs_emit_regs(&cs, A6XX_SP_FS_TEX_CONST(.qword = texture.iova)); in tu_emit_input_attachments()
1142 tu_cs_emit_regs(&cs, A6XX_SP_FS_TEX_COUNT(subpass->input_count * 2)); in tu_emit_input_attachments()
1144 assert(cs.cur == cs.end); /* validate draw state size */ in tu_emit_input_attachments()
1152 struct tu_cs *cs = &cmd->draw_cs; in tu_set_input_attachments() local
1154 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 6); in tu_set_input_attachments()
1155 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM, in tu_set_input_attachments()
1157 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM, in tu_set_input_attachments()
1165 struct tu_cs *cs = &cmd->draw_cs; in tu_emit_renderpass_begin() local
1167 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM); in tu_emit_renderpass_begin()
1169 tu6_emit_blit_scissor(cmd, cs, true); in tu_emit_renderpass_begin()
1172 tu_load_gmem_attachment(cmd, cs, i, false); in tu_emit_renderpass_begin()
1174 tu6_emit_blit_scissor(cmd, cs, false); in tu_emit_renderpass_begin()
1177 tu_clear_gmem_attachment(cmd, cs, i, info); in tu_emit_renderpass_begin()
1179 tu_cond_exec_end(cs); in tu_emit_renderpass_begin()
1181 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM); in tu_emit_renderpass_begin()
1184 tu_clear_sysmem_attachment(cmd, cs, i, info); in tu_emit_renderpass_begin()
1186 tu_cond_exec_end(cs); in tu_emit_renderpass_begin()
1190 tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs) in tu6_sysmem_render_begin() argument
1195 tu6_emit_window_scissor(cs, 0, 0, fb->width - 1, fb->height - 1); in tu6_sysmem_render_begin()
1196 tu6_emit_window_offset(cs, 0, 0); in tu6_sysmem_render_begin()
1198 tu6_emit_bin_size(cs, 0, 0, in tu6_sysmem_render_begin()
1201 tu6_emit_event_write(cmd, cs, LRZ_FLUSH); in tu6_sysmem_render_begin()
1203 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1); in tu6_sysmem_render_begin()
1204 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS)); in tu6_sysmem_render_begin()
1206 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1); in tu6_sysmem_render_begin()
1207 tu_cs_emit(cs, 0x0); in tu6_sysmem_render_begin()
1209 tu_emit_cache_flush_ccu(cmd, cs, TU_CMD_CCU_SYSMEM); in tu6_sysmem_render_begin()
1212 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false)); in tu6_sysmem_render_begin()
1214 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1); in tu6_sysmem_render_begin()
1215 tu_cs_emit(cs, 0x1); in tu6_sysmem_render_begin()
1217 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1); in tu6_sysmem_render_begin()
1218 tu_cs_emit(cs, 0x0); in tu6_sysmem_render_begin()
1220 tu_cs_sanity_check(cs); in tu6_sysmem_render_begin()
1224 tu6_sysmem_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs) in tu6_sysmem_render_end() argument
1229 tu6_emit_sysmem_resolves(cmd, cs, cmd->state.subpass); in tu6_sysmem_render_end()
1231 tu_cs_emit_call(cs, &cmd->draw_epilogue_cs); in tu6_sysmem_render_end()
1233 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1); in tu6_sysmem_render_end()
1234 tu_cs_emit(cs, 0x0); in tu6_sysmem_render_end()
1236 tu6_emit_event_write(cmd, cs, LRZ_FLUSH); in tu6_sysmem_render_end()
1238 tu_cs_sanity_check(cs); in tu6_sysmem_render_end()
1242 tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs) in tu6_tile_render_begin() argument
1246 tu6_emit_event_write(cmd, cs, LRZ_FLUSH); in tu6_tile_render_begin()
1248 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1); in tu6_tile_render_begin()
1249 tu_cs_emit(cs, 0x0); in tu6_tile_render_begin()
1251 tu_emit_cache_flush_ccu(cmd, cs, TU_CMD_CCU_GMEM); in tu6_tile_render_begin()
1256 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false)); in tu6_tile_render_begin()
1258 tu6_emit_bin_size(cs, fb->tile0.width, fb->tile0.height, in tu6_tile_render_begin()
1262 tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, true); in tu6_tile_render_begin()
1264 tu6_emit_binning_pass(cmd, cs); in tu6_tile_render_begin()
1267 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true)); in tu6_tile_render_begin()
1269 tu6_emit_bin_size(cs, fb->tile0.width, fb->tile0.height, in tu6_tile_render_begin()
1273 tu_cs_emit_regs(cs, in tu6_tile_render_begin()
1276 tu_cs_emit_regs(cs, in tu6_tile_render_begin()
1279 tu_cs_emit_regs(cs, in tu6_tile_render_begin()
1282 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1); in tu6_tile_render_begin()
1283 tu_cs_emit(cs, 0x1); in tu6_tile_render_begin()
1286 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false)); in tu6_tile_render_begin()
1288 tu6_emit_bin_size(cs, fb->tile0.width, fb->tile0.height, in tu6_tile_render_begin()
1292 tu_cs_sanity_check(cs); in tu6_tile_render_begin()
1296 tu6_render_tile(struct tu_cmd_buffer *cmd, struct tu_cs *cs) in tu6_render_tile() argument
1298 tu_cs_emit_call(cs, &cmd->draw_cs); in tu6_render_tile()
1301 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1); in tu6_render_tile()
1302 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS)); in tu6_render_tile()
1305 tu_cs_emit_call(cs, &cmd->tile_store_cs); in tu6_render_tile()
1308 tu_cs_emit_wfi(cs); in tu6_render_tile()
1309 tu_cs_emit_pkt7(&cmd->cs, CP_WAIT_FOR_ME, 0); in tu6_render_tile()
1313 cs, tu_copy_timestamp_buffer); in tu6_render_tile()
1316 tu_cs_sanity_check(cs); in tu6_render_tile()
1320 tu6_tile_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs) in tu6_tile_render_end() argument
1322 tu_cs_emit_call(cs, &cmd->draw_epilogue_cs); in tu6_tile_render_end()
1324 tu_cs_emit_regs(cs, in tu6_tile_render_end()
1327 tu6_emit_event_write(cmd, cs, LRZ_FLUSH); in tu6_tile_render_end()
1329 tu6_emit_event_write(cmd, cs, PC_CCU_RESOLVE_TS); in tu6_tile_render_end()
1331 tu_cs_sanity_check(cs); in tu6_tile_render_end()
1339 tu6_tile_render_begin(cmd, &cmd->cs); in tu_cmd_render_tiles()
1351 tu6_emit_tile_select(cmd, &cmd->cs, tx, ty, pipe, slot); in tu_cmd_render_tiles()
1353 trace_start_draw_ib_gmem(&cmd->trace, &cmd->cs); in tu_cmd_render_tiles()
1354 tu6_render_tile(cmd, &cmd->cs); in tu_cmd_render_tiles()
1355 trace_end_draw_ib_gmem(&cmd->trace, &cmd->cs); in tu_cmd_render_tiles()
1361 tu6_tile_render_end(cmd, &cmd->cs); in tu_cmd_render_tiles()
1363 trace_end_render_pass(&cmd->trace, &cmd->cs, fb); in tu_cmd_render_tiles()
1373 tu6_sysmem_render_begin(cmd, &cmd->cs); in tu_cmd_render_sysmem()
1375 trace_start_draw_ib_sysmem(&cmd->trace, &cmd->cs); in tu_cmd_render_sysmem()
1377 tu_cs_emit_call(&cmd->cs, &cmd->draw_cs); in tu_cmd_render_sysmem()
1379 trace_end_draw_ib_sysmem(&cmd->trace, &cmd->cs); in tu_cmd_render_sysmem()
1381 tu6_sysmem_render_end(cmd, &cmd->cs); in tu_cmd_render_sysmem()
1383 trace_end_render_pass(&cmd->trace, &cmd->cs, cmd->state.framebuffer); in tu_cmd_render_sysmem()
1424 tu_cs_init(&cmd_buffer->cs, device, TU_CS_MODE_GROW, 4096); in tu_create_cmd_buffer()
1440 tu_cs_finish(&cmd_buffer->cs); in tu_cmd_buffer_destroy()
1460 tu_cs_reset(&cmd_buffer->cs); in tu_reset_cmd_buffer()
1599 tu_cs_begin(&cmd_buffer->cs); in tu_BeginCommandBuffer()
1608 tu6_init_hw(cmd_buffer, &cmd_buffer->cs); in tu_BeginCommandBuffer()
1666 struct tu_cs cs; in tu_CmdBindVertexBuffers2EXT() local
1668 cmd->state.vertex_buffers.iova = tu_cs_draw_state(&cmd->sub_cs, &cs, 4 * MAX_VBS).iova; in tu_CmdBindVertexBuffers2EXT()
1685 tu_cs_emit_regs(&cs, in tu_CmdBindVertexBuffers2EXT()
1694 tu_cs_draw_state(&cmd->sub_cs, &cs, 2 * MAX_VBS).iova; in tu_CmdBindVertexBuffers2EXT()
1697 tu_cs_emit_regs(&cs, A6XX_VFD_FETCH_STRIDE(i, cmd->state.vb[i].stride)); in tu_CmdBindVertexBuffers2EXT()
1805 struct tu_cs *cs, state_cs; in tu_CmdBindDescriptorSets() local
1835 cs = &state_cs; in tu_CmdBindDescriptorSets()
1844 cs = &cmd->cs; in tu_CmdBindDescriptorSets()
1847 tu_cs_emit_pkt4(cs, sp_bindless_base_reg, 10); in tu_CmdBindDescriptorSets()
1848 tu_cs_emit_array(cs, (const uint32_t*) addr, 10); in tu_CmdBindDescriptorSets()
1849 tu_cs_emit_pkt4(cs, hlsq_bindless_base_reg, 10); in tu_CmdBindDescriptorSets()
1850 tu_cs_emit_array(cs, (const uint32_t*) addr, 10); in tu_CmdBindDescriptorSets()
1851 tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(.dword = hlsq_invalidate_value)); in tu_CmdBindDescriptorSets()
1854 assert(cs->cur == cs->end); /* validate draw state size */ in tu_CmdBindDescriptorSets()
1951 struct tu_cs *cs = &cmd->draw_cs; in tu_CmdBindTransformFeedbackBuffersEXT() local
1957 tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) | in tu_CmdBindTransformFeedbackBuffersEXT()
1974 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE(idx), 3); in tu_CmdBindTransformFeedbackBuffersEXT()
1975 tu_cs_emit_qw(cs, iova); in tu_CmdBindTransformFeedbackBuffersEXT()
1976 tu_cs_emit(cs, size + offset); in tu_CmdBindTransformFeedbackBuffersEXT()
1981 tu_cond_exec_end(cs); in tu_CmdBindTransformFeedbackBuffersEXT()
1992 struct tu_cs *cs = &cmd->draw_cs; in tu_CmdBeginTransformFeedbackEXT() local
1994 tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) | in tu_CmdBeginTransformFeedbackEXT()
2000 tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_OFFSET(i, cmd->state.streamout_offset[i])); in tu_CmdBeginTransformFeedbackEXT()
2012 tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3); in tu_CmdBeginTransformFeedbackEXT()
2013 tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx)) | in tu_CmdBeginTransformFeedbackEXT()
2016 tu_cs_emit_qw(cs, buf->bo->iova + counter_buffer_offset); in tu_CmdBeginTransformFeedbackEXT()
2019 tu_cs_emit_pkt7(cs, CP_REG_RMW, 3); in tu_CmdBeginTransformFeedbackEXT()
2020 tu_cs_emit(cs, CP_REG_RMW_0_DST_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx)) | in tu_CmdBeginTransformFeedbackEXT()
2022 tu_cs_emit(cs, 0xffffffff); in tu_CmdBeginTransformFeedbackEXT()
2023 tu_cs_emit(cs, offset); in tu_CmdBeginTransformFeedbackEXT()
2027 tu_cond_exec_end(cs); in tu_CmdBeginTransformFeedbackEXT()
2038 struct tu_cs *cs = &cmd->draw_cs; in tu_CmdEndTransformFeedbackEXT() local
2040 tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) | in tu_CmdEndTransformFeedbackEXT()
2047 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE(i), 2); in tu_CmdEndTransformFeedbackEXT()
2048 tu_cs_emit_qw(cs, global_iova(cmd, flush_base[i])); in tu_CmdEndTransformFeedbackEXT()
2049 tu6_emit_event_write(cmd, cs, FLUSH_SO_0 + i); in tu_CmdEndTransformFeedbackEXT()
2063 tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3); in tu_CmdEndTransformFeedbackEXT()
2064 tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) | in tu_CmdEndTransformFeedbackEXT()
2069 tu_cs_emit_qw(cs, global_iova(cmd, flush_base[idx])); in tu_CmdEndTransformFeedbackEXT()
2072 tu_cs_emit_pkt7(cs, CP_REG_RMW, 3); in tu_CmdEndTransformFeedbackEXT()
2073 tu_cs_emit(cs, CP_REG_RMW_0_DST_REG(REG_A6XX_CP_SCRATCH_REG(0)) | in tu_CmdEndTransformFeedbackEXT()
2075 tu_cs_emit(cs, 0xffffffff); in tu_CmdEndTransformFeedbackEXT()
2076 tu_cs_emit(cs, -offset); in tu_CmdEndTransformFeedbackEXT()
2079 tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3); in tu_CmdEndTransformFeedbackEXT()
2080 tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) | in tu_CmdEndTransformFeedbackEXT()
2082 tu_cs_emit_qw(cs, buf->bo->iova + counter_buffer_offset); in tu_CmdEndTransformFeedbackEXT()
2085 tu_cond_exec_end(cs); in tu_CmdEndTransformFeedbackEXT()
2138 tu_emit_cache_flush(cmd_buffer, &cmd_buffer->cs); in tu_EndCommandBuffer()
2141 tu_cs_end(&cmd_buffer->cs); in tu_EndCommandBuffer()
2154 struct tu_cs cs; in tu_cmd_dynamic_state() local
2157 cmd->state.dynamic_state[id] = tu_cs_draw_state(&cmd->sub_cs, &cs, size); in tu_cmd_dynamic_state()
2163 return cs; in tu_cmd_dynamic_state()
2168 return cs; in tu_cmd_dynamic_state()
2181 tu_cs_emit_state_ib(&cmd->cs, pipeline->program.state); in tu_CmdBindPipeline()
2195 struct tu_cs *cs = &cmd->draw_cs; in tu_CmdBindPipeline() local
2198 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * (7 + util_bitcount(mask))); in tu_CmdBindPipeline()
2199 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_CONFIG, pipeline->program.config_state); in tu_CmdBindPipeline()
2200 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM, pipeline->program.state); in tu_CmdBindPipeline()
2201 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_BINNING, pipeline->program.binning_state); in tu_CmdBindPipeline()
2202 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI, pipeline->vi.state); in tu_CmdBindPipeline()
2203 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI_BINNING, pipeline->vi.binning_state); in tu_CmdBindPipeline()
2204 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_RAST, pipeline->rast_state); in tu_CmdBindPipeline()
2205 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_BLEND, pipeline->blend_state); in tu_CmdBindPipeline()
2208 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + i, pipeline->dynamic_state[i]); in tu_CmdBindPipeline()
2279 struct tu_cs cs; in tu_CmdSetViewport() local
2284 cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_VIEWPORT, 8 + 10 * cmd->state.max_viewport); in tu_CmdSetViewport()
2285 tu6_emit_viewport(&cs, cmd->state.viewport, cmd->state.max_viewport); in tu_CmdSetViewport()
2295 struct tu_cs cs; in tu_CmdSetScissor() local
2300 cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_SCISSOR, 1 + 2 * cmd->state.max_scissor); in tu_CmdSetScissor()
2301 tu6_emit_scissor(&cs, cmd->state.scissor, cmd->state.max_scissor); in tu_CmdSetScissor()
2322 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_DEPTH_BIAS, 4); in tu_CmdSetDepthBias() local
2324 tu6_emit_depth_bias(&cs, depthBiasConstantFactor, depthBiasClamp, depthBiasSlopeFactor); in tu_CmdSetDepthBias()
2332 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_BLEND_CONSTANTS, 5); in tu_CmdSetBlendConstants() local
2334 tu_cs_emit_pkt4(&cs, REG_A6XX_RB_BLEND_RED_F32, 4); in tu_CmdSetBlendConstants()
2335 tu_cs_emit_array(&cs, (const uint32_t *) blendConstants, 4); in tu_CmdSetBlendConstants()
2344 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_DEPTH_BOUNDS, 3); in tu_CmdSetDepthBounds() local
2346 tu_cs_emit_regs(&cs, in tu_CmdSetDepthBounds()
2366 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK, 2); in tu_CmdSetStencilCompareMask() local
2370 tu_cs_emit_regs(&cs, A6XX_RB_STENCILMASK(.dword = cmd->state.dynamic_stencil_mask)); in tu_CmdSetStencilCompareMask()
2379 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK, 2); in tu_CmdSetStencilWriteMask() local
2383 tu_cs_emit_regs(&cs, A6XX_RB_STENCILWRMASK(.dword = cmd->state.dynamic_stencil_wrmask)); in tu_CmdSetStencilWriteMask()
2394 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_STENCIL_REFERENCE, 2); in tu_CmdSetStencilReference() local
2398 tu_cs_emit_regs(&cs, A6XX_RB_STENCILREF(.dword = cmd->state.dynamic_stencil_ref)); in tu_CmdSetStencilReference()
2406 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS, 9); in tu_CmdSetSampleLocationsEXT() local
2410 tu6_emit_sample_locations(&cs, pSampleLocationsInfo); in tu_CmdSetSampleLocationsEXT()
2956 tu_emit_cache_flush(cmd, &cmd->cs); in tu_CmdExecuteCommands()
2964 assert(tu_cs_is_empty(&secondary->cs)); in tu_CmdExecuteCommands()
2989 tu_cs_add_entries(&cmd->cs, &secondary->cs); in tu_CmdExecuteCommands()
3167 trace_start_render_pass(&cmd->trace, &cmd->cs); in tu_CmdBeginRenderPass2()
3193 tu6_clear_lrz(cmd, &cmd->cs, image, &pRenderPassBegin->pClearValues[a]); in tu_CmdBeginRenderPass2()
3227 struct tu_cs *cs = &cmd->draw_cs; in tu_CmdNextSubpass2() local
3239 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM); in tu_CmdNextSubpass2()
3242 tu6_emit_blit_scissor(cmd, cs, true); in tu_CmdNextSubpass2()
3251 tu_store_gmem_attachment(cmd, cs, a, gmem_a); in tu_CmdNextSubpass2()
3261 tu_load_gmem_attachment(cmd, cs, a, true); in tu_CmdNextSubpass2()
3265 tu_cond_exec_end(cs); in tu_CmdNextSubpass2()
3267 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM); in tu_CmdNextSubpass2()
3269 tu6_emit_sysmem_resolves(cmd, cs, subpass); in tu_CmdNextSubpass2()
3271 tu_cond_exec_end(cs); in tu_CmdNextSubpass2()
3280 tu6_emit_zs(cmd, cmd->state.subpass, cs); in tu_CmdNextSubpass2()
3281 tu6_emit_mrt(cmd, cmd->state.subpass, cs); in tu_CmdNextSubpass2()
3283 tu6_emit_msaa(cs, cmd->state.subpass->samples, cmd->state.line_mode); in tu_CmdNextSubpass2()
3284 tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, false); in tu_CmdNextSubpass2()
3339 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline, in tu6_emit_user_consts() argument
3352 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_units * 4); in tu6_emit_user_consts()
3353 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) | in tu6_emit_user_consts()
3358 tu_cs_emit(cs, 0); in tu6_emit_user_consts()
3359 tu_cs_emit(cs, 0); in tu6_emit_user_consts()
3361 tu_cs_emit(cs, push_constants[i + offset * 4]); in tu6_emit_user_consts()
3407 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + zero_size / 4); in tu6_emit_user_consts()
3408 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(zero_offset / 16) | in tu6_emit_user_consts()
3413 tu_cs_emit_qw(cs, 0); in tu6_emit_user_consts()
3415 tu_cs_emit(cs, 0); in tu6_emit_user_consts()
3422 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3); in tu6_emit_user_consts()
3423 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) | in tu6_emit_user_consts()
3428 tu_cs_emit_qw(cs, va + offset); in tu6_emit_user_consts()
3443 struct tu_cs cs; in tu6_emit_consts() local
3444 tu_cs_begin_sub_stream(&cmd->sub_cs, dwords, &cs); in tu6_emit_consts()
3446 tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants); in tu6_emit_consts()
3448 return tu_cs_end_draw_state(&cmd->sub_cs, &cs); in tu6_emit_consts()
3464 struct tu_cs cs; in tu6_emit_consts_geom() local
3465 tu_cs_begin_sub_stream(&cmd->sub_cs, dwords, &cs); in tu6_emit_consts_geom()
3468 tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants); in tu6_emit_consts_geom()
3470 return tu_cs_end_draw_state(&cmd->sub_cs, &cs); in tu6_emit_consts_geom()
3529 struct tu_cs cs; in tu6_emit_tess_consts() local
3530 VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 16, &cs); in tu6_emit_tess_consts()
3555 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4); in tu6_emit_tess_consts()
3556 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(pipeline->tess.hs_bo_regid) | in tu6_emit_tess_consts()
3561 tu_cs_emit(&cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0)); in tu6_emit_tess_consts()
3562 tu_cs_emit(&cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0)); in tu6_emit_tess_consts()
3563 tu_cs_emit_qw(&cs, tess_param_iova); in tu6_emit_tess_consts()
3564 tu_cs_emit_qw(&cs, tess_factor_iova); in tu6_emit_tess_consts()
3568 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4); in tu6_emit_tess_consts()
3569 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(pipeline->tess.ds_bo_regid) | in tu6_emit_tess_consts()
3574 tu_cs_emit(&cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0)); in tu6_emit_tess_consts()
3575 tu_cs_emit(&cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0)); in tu6_emit_tess_consts()
3576 tu_cs_emit_qw(&cs, tess_param_iova); in tu6_emit_tess_consts()
3577 tu_cs_emit_qw(&cs, tess_factor_iova); in tu6_emit_tess_consts()
3582 *state = tu_cs_end_draw_state(&cmd->sub_cs, &cs); in tu6_emit_tess_consts()
3827 struct tu_cs cs; in tu6_build_depth_plane_z_mode() local
3828 struct tu_draw_state ds = tu_cs_draw_state(&cmd->sub_cs, &cs, 4); in tu6_build_depth_plane_z_mode()
3847 tu_cs_emit_pkt4(&cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1); in tu6_build_depth_plane_z_mode()
3848 tu_cs_emit(&cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode)); in tu6_build_depth_plane_z_mode()
3850 tu_cs_emit_pkt4(&cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1); in tu6_build_depth_plane_z_mode()
3851 tu_cs_emit(&cs, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode)); in tu6_build_depth_plane_z_mode()
3857 struct tu_cs *cs, in tu6_draw_common() argument
3865 tu_emit_cache_flush_renderpass(cmd, cs); in tu6_draw_common()
3871 tu_cs_emit_regs(cs, A6XX_PC_PRIMITIVE_CNTL_0( in tu6_draw_common()
3897 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_RASTERIZER_DISCARD, 4); in tu6_draw_common() local
3898 tu_cs_emit_regs(&cs, A6XX_PC_RASTER_CNTL(.dword = cmd->state.pc_raster_cntl)); in tu6_draw_common()
3899 tu_cs_emit_regs(&cs, A6XX_VPC_UNKNOWN_9107(.dword = cmd->state.vpc_unknown_9107)); in tu6_draw_common()
3903 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_GRAS_SU_CNTL, 2); in tu6_draw_common() local
3904 tu_cs_emit_regs(&cs, A6XX_GRAS_SU_CNTL(.dword = cmd->state.gras_su_cntl)); in tu6_draw_common()
3908 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_RB_DEPTH_CNTL, 2); in tu6_draw_common() local
3922 tu_cs_emit_regs(&cs, A6XX_RB_DEPTH_CNTL(.dword = rb_depth_cntl)); in tu6_draw_common()
3926 struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_RB_STENCIL_CNTL, 2); in tu6_draw_common() local
3927 tu_cs_emit_regs(&cs, A6XX_RB_STENCIL_CONTROL(.dword = cmd->state.rb_stencil_cntl)); in tu6_draw_common()
3950 tu_cs_emit_wfi(cs); in tu6_draw_common()
3952 tu_cs_emit_regs(cs, A6XX_PC_TESSFACTOR_ADDR(.qword = tess_factor_iova)); in tu6_draw_common()
3954 tu_cs_emit_pkt7(cs, CP_SET_SUBDRAW_SIZE, 1); in tu6_draw_common()
3955 tu_cs_emit(cs, draw_count); in tu6_draw_common()
3969 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * (TU_DRAW_STATE_COUNT - 2)); in tu6_draw_common()
3971 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_CONFIG, pipeline->program.config_state); in tu6_draw_common()
3972 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM, pipeline->program.state); in tu6_draw_common()
3973 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_BINNING, pipeline->program.binning_state); in tu6_draw_common()
3974 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_TESS, tess_consts); in tu6_draw_common()
3975 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI, pipeline->vi.state); in tu6_draw_common()
3976 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI_BINNING, pipeline->vi.binning_state); in tu6_draw_common()
3977 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_RAST, pipeline->rast_state); in tu6_draw_common()
3978 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_BLEND, pipeline->blend_state); in tu6_draw_common()
3979 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_SHADER_GEOM_CONST, cmd->state.shader_const[0]); in tu6_draw_common()
3980 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_FS_CONST, cmd->state.shader_const[1]); in tu6_draw_common()
3981 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS, cmd->state.desc_sets); in tu6_draw_common()
3982 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS_LOAD, pipeline->load_state); in tu6_draw_common()
3983 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VB, cmd->state.vertex_buffers); in tu6_draw_common()
3984 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params); in tu6_draw_common()
3985 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_LRZ, cmd->state.lrz.state); in tu6_draw_common()
3986 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DEPTH_PLANE, cmd->state.depth_plane_state); in tu6_draw_common()
3989 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + i, in tu6_draw_common()
4014 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_count); in tu6_draw_common()
4019 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_TESS, tess_consts); in tu6_draw_common()
4021 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_SHADER_GEOM_CONST, cmd->state.shader_const[0]); in tu6_draw_common()
4022 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_FS_CONST, cmd->state.shader_const[1]); in tu6_draw_common()
4025 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS_LOAD, pipeline->load_state); in tu6_draw_common()
4027 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VB, cmd->state.vertex_buffers); in tu6_draw_common()
4029 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + TU_DYNAMIC_STATE_VB_STRIDE, in tu6_draw_common()
4033 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params); in tu6_draw_common()
4036 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_LRZ, cmd->state.lrz.state); in tu6_draw_common()
4037 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DEPTH_PLANE, cmd->state.depth_plane_state); in tu6_draw_common()
4041 tu_cs_sanity_check(cs); in tu6_draw_common()
4146 struct tu_cs cs; in tu6_emit_vs_params() local
4147 VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 3 + (offset ? 8 : 0), &cs); in tu6_emit_vs_params()
4153 tu_cs_emit_regs(&cs, in tu6_emit_vs_params()
4158 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4); in tu6_emit_vs_params()
4159 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(offset) | in tu6_emit_vs_params()
4164 tu_cs_emit(&cs, 0); in tu6_emit_vs_params()
4165 tu_cs_emit(&cs, 0); in tu6_emit_vs_params()
4167 tu_cs_emit(&cs, 0); in tu6_emit_vs_params()
4168 tu_cs_emit(&cs, vertex_offset); in tu6_emit_vs_params()
4169 tu_cs_emit(&cs, first_instance); in tu6_emit_vs_params()
4170 tu_cs_emit(&cs, 0); in tu6_emit_vs_params()
4176 struct tu_cs_entry entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs); in tu6_emit_vs_params()
4190 struct tu_cs *cs = &cmd->draw_cs; in tu_CmdDraw() local
4194 tu6_draw_common(cmd, cs, false, vertexCount); in tu_CmdDraw()
4196 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3); in tu_CmdDraw()
4197 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX)); in tu_CmdDraw()
4198 tu_cs_emit(cs, instanceCount); in tu_CmdDraw()
4199 tu_cs_emit(cs, vertexCount); in tu_CmdDraw()
4211 struct tu_cs *cs = &cmd->draw_cs; in tu_CmdDrawIndexed() local
4215 tu6_draw_common(cmd, cs, true, indexCount); in tu_CmdDrawIndexed()
4217 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7); in tu_CmdDrawIndexed()
4218 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA)); in tu_CmdDrawIndexed()
4219 tu_cs_emit(cs, instanceCount); in tu_CmdDrawIndexed()
4220 tu_cs_emit(cs, indexCount); in tu_CmdDrawIndexed()
4221 tu_cs_emit(cs, firstIndex); in tu_CmdDrawIndexed()
4222 tu_cs_emit_qw(cs, cmd->state.index_va); in tu_CmdDrawIndexed()
4223 tu_cs_emit(cs, cmd->state.max_index_count); in tu_CmdDrawIndexed()
4249 struct tu_cs *cs = &cmd->draw_cs; in tu_CmdDrawIndirect() local
4256 tu6_draw_common(cmd, cs, false, 0); in tu_CmdDrawIndirect()
4258 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 6); in tu_CmdDrawIndirect()
4259 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX)); in tu_CmdDrawIndirect()
4260 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_NORMAL) | in tu_CmdDrawIndirect()
4262 tu_cs_emit(cs, drawCount); in tu_CmdDrawIndirect()
4263 tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + offset); in tu_CmdDrawIndirect()
4264 tu_cs_emit(cs, stride); in tu_CmdDrawIndirect()
4276 struct tu_cs *cs = &cmd->draw_cs; in tu_CmdDrawIndexedIndirect() local
4283 tu6_draw_common(cmd, cs, true, 0); in tu_CmdDrawIndexedIndirect()
4285 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 9); in tu_CmdDrawIndexedIndirect()
4286 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA)); in tu_CmdDrawIndexedIndirect()
4287 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDEXED) | in tu_CmdDrawIndexedIndirect()
4289 tu_cs_emit(cs, drawCount); in tu_CmdDrawIndexedIndirect()
4290 tu_cs_emit_qw(cs, cmd->state.index_va); in tu_CmdDrawIndexedIndirect()
4291 tu_cs_emit(cs, cmd->state.max_index_count); in tu_CmdDrawIndexedIndirect()
4292 tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + offset); in tu_CmdDrawIndexedIndirect()
4293 tu_cs_emit(cs, stride); in tu_CmdDrawIndexedIndirect()
4308 struct tu_cs *cs = &cmd->draw_cs; in tu_CmdDrawIndirectCount() local
4319 tu6_draw_common(cmd, cs, false, 0); in tu_CmdDrawIndirectCount()
4321 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 8); in tu_CmdDrawIndirectCount()
4322 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX)); in tu_CmdDrawIndirectCount()
4323 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT) | in tu_CmdDrawIndirectCount()
4325 tu_cs_emit(cs, drawCount); in tu_CmdDrawIndirectCount()
4326 tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + offset); in tu_CmdDrawIndirectCount()
4327 tu_cs_emit_qw(cs, count_buf->bo->iova + count_buf->bo_offset + countBufferOffset); in tu_CmdDrawIndirectCount()
4328 tu_cs_emit(cs, stride); in tu_CmdDrawIndirectCount()
4343 struct tu_cs *cs = &cmd->draw_cs; in tu_CmdDrawIndexedIndirectCount() local
4349 tu6_draw_common(cmd, cs, true, 0); in tu_CmdDrawIndexedIndirectCount()
4351 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 11); in tu_CmdDrawIndexedIndirectCount()
4352 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA)); in tu_CmdDrawIndexedIndirectCount()
4353 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT_INDEXED) | in tu_CmdDrawIndexedIndirectCount()
4355 tu_cs_emit(cs, drawCount); in tu_CmdDrawIndexedIndirectCount()
4356 tu_cs_emit_qw(cs, cmd->state.index_va); in tu_CmdDrawIndexedIndirectCount()
4357 tu_cs_emit(cs, cmd->state.max_index_count); in tu_CmdDrawIndexedIndirectCount()
4358 tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + offset); in tu_CmdDrawIndexedIndirectCount()
4359 tu_cs_emit_qw(cs, count_buf->bo->iova + count_buf->bo_offset + countBufferOffset); in tu_CmdDrawIndexedIndirectCount()
4360 tu_cs_emit(cs, stride); in tu_CmdDrawIndexedIndirectCount()
4374 struct tu_cs *cs = &cmd->draw_cs; in tu_CmdDrawIndirectByteCountEXT() local
4385 tu6_draw_common(cmd, cs, false, 0); in tu_CmdDrawIndirectByteCountEXT()
4387 tu_cs_emit_pkt7(cs, CP_DRAW_AUTO, 6); in tu_CmdDrawIndirectByteCountEXT()
4388 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_XFB)); in tu_CmdDrawIndirectByteCountEXT()
4389 tu_cs_emit(cs, instanceCount); in tu_CmdDrawIndirectByteCountEXT()
4390 tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + counterBufferOffset); in tu_CmdDrawIndirectByteCountEXT()
4391 tu_cs_emit(cs, counterOffset); in tu_CmdDrawIndirectByteCountEXT()
4392 tu_cs_emit(cs, vertexStride); in tu_CmdDrawIndirectByteCountEXT()
4421 struct tu_cs *cs, struct tu_pipeline *pipeline, in tu_emit_compute_driver_params() argument
4453 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_consts); in tu_emit_compute_driver_params()
4454 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) | in tu_emit_compute_driver_params()
4459 tu_cs_emit(cs, 0); in tu_emit_compute_driver_params()
4460 tu_cs_emit(cs, 0); in tu_emit_compute_driver_params()
4463 tu_cs_emit(cs, driver_params[i]); in tu_emit_compute_driver_params()
4465 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3); in tu_emit_compute_driver_params()
4466 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) | in tu_emit_compute_driver_params()
4471 tu_cs_emit_qw(cs, tu_buffer_iova(info->indirect) + info->indirect_offset); in tu_emit_compute_driver_params()
4480 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 5); in tu_emit_compute_driver_params()
4481 tu_cs_emit(cs, 0); in tu_emit_compute_driver_params()
4482 tu_cs_emit_qw(cs, global_iova(cmd, cs_indirect_xyz[i])); in tu_emit_compute_driver_params()
4483 tu_cs_emit_qw(cs, indirect_iova + i * 4); in tu_emit_compute_driver_params()
4486 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0); in tu_emit_compute_driver_params()
4487 tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE); in tu_emit_compute_driver_params()
4489 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3); in tu_emit_compute_driver_params()
4490 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) | in tu_emit_compute_driver_params()
4495 tu_cs_emit_qw(cs, global_iova(cmd, cs_indirect_xyz[0])); in tu_emit_compute_driver_params()
4502 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 7); in tu_emit_compute_driver_params()
4503 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset + (IR3_DP_BASE_GROUP_X / 4)) | in tu_emit_compute_driver_params()
4508 tu_cs_emit_qw(cs, 0); in tu_emit_compute_driver_params()
4509 tu_cs_emit(cs, 0); /* BASE_GROUP_X */ in tu_emit_compute_driver_params()
4510 tu_cs_emit(cs, 0); /* BASE_GROUP_Y */ in tu_emit_compute_driver_params()
4511 tu_cs_emit(cs, 0); /* BASE_GROUP_Z */ in tu_emit_compute_driver_params()
4512 tu_cs_emit(cs, subgroup_size); in tu_emit_compute_driver_params()
4515 tu_cs_emit(cs, 0); /* LOCAL_GROUP_SIZE_X */ in tu_emit_compute_driver_params()
4516 tu_cs_emit(cs, 0); /* LOCAL_GROUP_SIZE_Y */ in tu_emit_compute_driver_params()
4517 tu_cs_emit(cs, 0); /* LOCAL_GROUP_SIZE_Z */ in tu_emit_compute_driver_params()
4518 tu_cs_emit(cs, subgroup_shift); in tu_emit_compute_driver_params()
4531 struct tu_cs *cs = &cmd->cs; in tu_dispatch() local
4539 tu_emit_cache_flush(cmd, cs); in tu_dispatch()
4542 tu_cs_emit_state_ib(cs, in tu_dispatch()
4545 tu_emit_compute_driver_params(cmd, cs, pipeline, info); in tu_dispatch()
4548 tu_cs_emit_state_ib(cs, pipeline->load_state); in tu_dispatch()
4552 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1); in tu_dispatch()
4553 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE)); in tu_dispatch()
4557 tu_cs_emit_regs(cs, in tu_dispatch()
4569 tu_cs_emit_regs(cs, in tu_dispatch()
4574 trace_start_compute(&cmd->trace, cs); in tu_dispatch()
4579 tu_cs_emit_pkt7(cs, CP_EXEC_CS_INDIRECT, 4); in tu_dispatch()
4580 tu_cs_emit(cs, 0x00000000); in tu_dispatch()
4581 tu_cs_emit_qw(cs, iova); in tu_dispatch()
4582 tu_cs_emit(cs, in tu_dispatch()
4587 tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4); in tu_dispatch()
4588 tu_cs_emit(cs, 0x00000000); in tu_dispatch()
4589 tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(info->blocks[0])); in tu_dispatch()
4590 tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(info->blocks[1])); in tu_dispatch()
4591 tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(info->blocks[2])); in tu_dispatch()
4594 trace_end_compute(&cmd->trace, cs, in tu_dispatch()
4599 tu_cs_emit_wfi(cs); in tu_dispatch()
4671 tu_disable_draw_states(cmd_buffer, &cmd_buffer->cs); in tu_CmdEndRenderPass2()
4719 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs; in tu_barrier() local
4804 tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6); in tu_barrier()
4805 tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) | in tu_barrier()
4807 tu_cs_emit_qw(cs, event->bo.iova); /* POLL_ADDR_LO/HI */ in tu_barrier()
4808 tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(1)); in tu_barrier()
4809 tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0u)); in tu_barrier()
4810 tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20)); in tu_barrier()
4843 struct tu_cs *cs = &cmd->cs; in write_event() local
4848 tu_emit_cache_flush(cmd, cs); in write_event()
4858 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3); in write_event()
4859 tu_cs_emit_qw(cs, event->bo.iova); /* ADDR_LO/HI */ in write_event()
4860 tu_cs_emit(cs, value); in write_event()
4863 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 4); in write_event()
4864 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS)); in write_event()
4865 tu_cs_emit_qw(cs, event->bo.iova); in write_event()
4866 tu_cs_emit(cs, value); in write_event()
4935 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs; in tu_CmdBeginConditionalRenderingEXT() local
4937 tu_cs_emit_pkt7(cs, CP_DRAW_PRED_ENABLE_GLOBAL, 1); in tu_CmdBeginConditionalRenderingEXT()
4938 tu_cs_emit(cs, 1); in tu_CmdBeginConditionalRenderingEXT()
4942 tu_emit_cache_flush_renderpass(cmd, cs); in tu_CmdBeginConditionalRenderingEXT()
4944 tu_emit_cache_flush(cmd, cs); in tu_CmdBeginConditionalRenderingEXT()
4954 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 5); in tu_CmdBeginConditionalRenderingEXT()
4955 tu_cs_emit(cs, 0); in tu_CmdBeginConditionalRenderingEXT()
4956 tu_cs_emit_qw(cs, global_iova(cmd, predicate)); in tu_CmdBeginConditionalRenderingEXT()
4957 tu_cs_emit_qw(cs, iova); in tu_CmdBeginConditionalRenderingEXT()
4959 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0); in tu_CmdBeginConditionalRenderingEXT()
4960 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0); in tu_CmdBeginConditionalRenderingEXT()
4963 tu_cs_emit_pkt7(cs, CP_DRAW_PRED_SET, 3); in tu_CmdBeginConditionalRenderingEXT()
4964 tu_cs_emit(cs, CP_DRAW_PRED_SET_0_SRC(PRED_SRC_MEM) | in tu_CmdBeginConditionalRenderingEXT()
4966 tu_cs_emit_qw(cs, global_iova(cmd, predicate)); in tu_CmdBeginConditionalRenderingEXT()
4976 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs; in tu_CmdEndConditionalRenderingEXT() local
4978 tu_cs_emit_pkt7(cs, CP_DRAW_PRED_ENABLE_GLOBAL, 1); in tu_CmdEndConditionalRenderingEXT()
4979 tu_cs_emit(cs, 0); in tu_CmdEndConditionalRenderingEXT()