Lines Matching refs:GENX
476 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in _iris_emit_lri()
481 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
486 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_REG), lrr) { in _iris_emit_lrr()
530 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { in iris_load_register_mem32()
555 iris_emit_cmd(batch, GENX(MI_STORE_REGISTER_MEM), srm) { in iris_store_register_mem32()
578 iris_emit_cmd(batch, GENX(MI_STORE_DATA_IMM), sdi) { in iris_store_data_imm32()
595 _iris_pack_command(batch, GENX(MI_STORE_DATA_IMM), map, sdi) { in iris_store_data_imm64()
616 iris_emit_cmd(batch, GENX(MI_COPY_MEM_MEM), cp) { in iris_copy_mem_mem()
640 iris_emit_cmd(batch, GENX(3DSTATE_CC_STATE_POINTERS), t); in emit_pipeline_select()
668 iris_emit_cmd(batch, GENX(PIPELINE_SELECT), sel) { in emit_pipeline_select()
688 iris_emit_reg(batch, GENX(SLICE_COMMON_ECO_CHICKEN1), reg) { in init_glk_barrier_mode()
709 iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) { in init_state_base_address()
751 #define L3_ALLOCATION_REG GENX(L3ALLOC) in iris_emit_l3_config()
752 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num) in iris_emit_l3_config()
754 #define L3_ALLOCATION_REG GENX(L3CNTLREG) in iris_emit_l3_config()
755 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num) in iris_emit_l3_config()
793 iris_emit_reg(batch, GENX(CS_CHICKEN1), reg) { in iris_enable_obj_preemption()
852 unsigned size = GENX(SLICE_HASH_TABLE_length) * 4; in gfx11_upload_pixel_hashing_tables()
861 struct GENX(SLICE_HASH_TABLE) table; in gfx11_upload_pixel_hashing_tables()
864 GENX(SLICE_HASH_TABLE_pack)(NULL, map, &table); in gfx11_upload_pixel_hashing_tables()
866 iris_emit_cmd(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) { in gfx11_upload_pixel_hashing_tables()
871 iris_emit_cmd(batch, GENX(3DSTATE_3D_MODE), mode) { in gfx11_upload_pixel_hashing_tables()
900 iris_emit_cmd(batch, GENX(3DSTATE_SUBSLICE_HASH_TABLE), p) { in gfx12_upload_pixel_hashing_tables()
918 iris_emit_cmd(batch, GENX(3DSTATE_3D_MODE), p) { in gfx12_upload_pixel_hashing_tables()
946 iris_emit_cmd(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc) { in iris_alloc_push_constants()
968 iris_emit_reg(batch, GENX(SAMPLER_MODE), reg) { in iris_init_common_context()
974 iris_emit_reg(batch, GENX(HALF_SLICE_CHICKEN7), reg) { in iris_init_common_context()
1003 iris_emit_reg(batch, GENX(CS_DEBUG_MODE2), reg) { in iris_init_render_context()
1008 iris_emit_reg(batch, GENX(INSTPM), reg) { in iris_init_render_context()
1015 iris_emit_reg(batch, GENX(CACHE_MODE_1), reg) { in iris_init_render_context()
1029 iris_emit_reg(batch, GENX(TCCNTLREG), reg) { in iris_init_render_context()
1040 iris_emit_reg(batch, GENX(CACHE_MODE_0), reg) { in iris_init_render_context()
1058 iris_emit_cmd(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) { in iris_init_render_context()
1064 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLE_PATTERN), pat) { in iris_init_render_context()
1075 iris_emit_cmd(batch, GENX(3DSTATE_AA_LINE_PARAMETERS), foo); in iris_init_render_context()
1078 iris_emit_cmd(batch, GENX(3DSTATE_WM_CHROMAKEY), foo); in iris_init_render_context()
1081 iris_emit_cmd(batch, GENX(3DSTATE_WM_HZ_OP), foo); in iris_init_render_context()
1085 iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_OFFSET), foo); in iris_init_render_context()
1138 uint32_t state[GENX(VERTEX_BUFFER_STATE_length)];
1148 uint32_t packets[GENX(3DSTATE_DEPTH_BUFFER_length) +
1149 GENX(3DSTATE_STENCIL_BUFFER_length) +
1150 GENX(3DSTATE_HIER_DEPTH_BUFFER_length) +
1151 GENX(3DSTATE_CLEAR_PARAMS_length)];
1170 uint32_t last_index_buffer[GENX(3DSTATE_INDEX_BUFFER_length)];
1174 uint32_t so_buffers[4 * GENX(3DSTATE_SO_BUFFER_length)];
1217 uint32_t ps_blend[GENX(3DSTATE_PS_BLEND_length)];
1220 uint32_t blend_state[GENX(BLEND_STATE_length) +
1221 BRW_MAX_DRAW_BUFFERS * GENX(BLEND_STATE_ENTRY_length)];
1259 uint32_t *blend_entry = cso->blend_state + GENX(BLEND_STATE_length); in iris_create_blend_state()
1292 iris_pack_state(GENX(BLEND_STATE_ENTRY), blend_entry, be) { in iris_create_blend_state()
1317 blend_entry += GENX(BLEND_STATE_ENTRY_length); in iris_create_blend_state()
1320 iris_pack_command(GENX(3DSTATE_PS_BLEND), cso->ps_blend, pb) { in iris_create_blend_state()
1342 iris_pack_state(GENX(BLEND_STATE), cso->blend_state, bs) { in iris_create_blend_state()
1401 uint32_t wmds[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
1404 uint32_t depth_bounds[GENX(3DSTATE_DEPTH_BOUNDS_length)];
1447 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), cso->wmds, wmds) { in iris_create_zsa_state()
1477 iris_pack_command(GENX(3DSTATE_DEPTH_BOUNDS), cso->depth_bounds, depth_bounds) { in iris_create_zsa_state()
1682 iris_emit_reg(batch, GENX(CACHE_MODE_1), reg) { in genX()
1707 uint32_t sf[GENX(3DSTATE_SF_length)];
1708 uint32_t clip[GENX(3DSTATE_CLIP_length)];
1709 uint32_t raster[GENX(3DSTATE_RASTER_length)];
1710 uint32_t wm[GENX(3DSTATE_WM_length)];
1711 uint32_t line_stipple[GENX(3DSTATE_LINE_STIPPLE_length)];
1810 iris_pack_command(GENX(3DSTATE_SF), cso->sf, sf) { in iris_create_rasterizer_state()
1831 iris_pack_command(GENX(3DSTATE_RASTER), cso->raster, rr) { in iris_create_rasterizer_state()
1856 iris_pack_command(GENX(3DSTATE_CLIP), cso->clip, cl) { in iris_create_rasterizer_state()
1878 iris_pack_command(GENX(3DSTATE_WM), cso->wm, wm) { in iris_create_rasterizer_state()
1892 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE), cso->line_stipple, line) { in iris_create_rasterizer_state()
1970 uint32_t sampler_state[GENX(SAMPLER_STATE_length)];
2013 iris_pack_state(GENX(SAMPLER_STATE), cso->sampler_state, samp) { in iris_create_sampler_state()
2119 unsigned size = count * 4 * GENX(SAMPLER_STATE_length); in iris_upload_sampler_states()
2143 memset(map, 0, 4 * GENX(SAMPLER_STATE_length)); in iris_upload_sampler_states()
2145 memcpy(map, state->sampler_state, 4 * GENX(SAMPLER_STATE_length)); in iris_upload_sampler_states()
2181 uint32_t dynamic[GENX(SAMPLER_STATE_length)]; in iris_upload_sampler_states()
2182 iris_pack_state(GENX(SAMPLER_STATE), dynamic, dyns) { in iris_upload_sampler_states()
2186 for (uint32_t j = 0; j < GENX(SAMPLER_STATE_length); j++) in iris_upload_sampler_states()
2190 map += GENX(SAMPLER_STATE_length); in iris_upload_sampler_states()
2261 const unsigned surf_size = 4 * GENX(RENDER_SURFACE_STATE_length); in alloc_surface_states()
2286 const unsigned surf_size = 4 * GENX(RENDER_SURFACE_STATE_length); in upload_surface_states()
2311 STATIC_ASSERT(GENX(RENDER_SURFACE_STATE_SurfaceBaseAddress_start) % 64 == 0); in update_surface_state_addrs()
2312 STATIC_ASSERT(GENX(RENDER_SURFACE_STATE_SurfaceBaseAddress_bits) == 64); in update_surface_state_addrs()
2314 …uint64_t *ss_addr = (uint64_t *) &surf_state->cpu[GENX(RENDER_SURFACE_STATE_SurfaceBaseAddress_sta… in update_surface_state_addrs()
3175 4 * GENX(RENDER_SURFACE_STATE_length), 64); in iris_set_framebuffer_state()
3472 iris_pack_state(GENX(VERTEX_BUFFER_STATE), state->state, vb) { in iris_set_vertex_buffers()
3505 uint32_t vertex_elements[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length)];
3506 uint32_t vf_instancing[33 * GENX(3DSTATE_VF_INSTANCING_length)];
3507 uint32_t edgeflag_ve[GENX(VERTEX_ELEMENT_STATE_length)];
3508 uint32_t edgeflag_vfi[GENX(3DSTATE_VF_INSTANCING_length)];
3535 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS), cso->vertex_elements, ve) { in iris_create_vertex_elements()
3537 1 + GENX(VERTEX_ELEMENT_STATE_length) * MAX2(count, 1) - 2; in iris_create_vertex_elements()
3544 iris_pack_state(GENX(VERTEX_ELEMENT_STATE), ve_pack_dest, ve) { in iris_create_vertex_elements()
3553 iris_pack_command(GENX(3DSTATE_VF_INSTANCING), vfi_pack_dest, vi) { in iris_create_vertex_elements()
3572 iris_pack_state(GENX(VERTEX_ELEMENT_STATE), ve_pack_dest, ve) { in iris_create_vertex_elements()
3584 iris_pack_command(GENX(3DSTATE_VF_INSTANCING), vfi_pack_dest, vi) { in iris_create_vertex_elements()
3590 ve_pack_dest += GENX(VERTEX_ELEMENT_STATE_length); in iris_create_vertex_elements()
3591 vfi_pack_dest += GENX(3DSTATE_VF_INSTANCING_length); in iris_create_vertex_elements()
3601 iris_pack_state(GENX(VERTEX_ELEMENT_STATE), cso->edgeflag_ve, ve) { in iris_create_vertex_elements()
3612 iris_pack_command(GENX(3DSTATE_VF_INSTANCING), cso->edgeflag_vfi, vi) { in iris_create_vertex_elements()
3753 so_buffers += GENX(3DSTATE_SO_BUFFER_length)) { in iris_set_stream_output_targets()
3759 iris_pack_command(GENX(3DSTATE_SO_BUFFER), so_buffers, sob) { in iris_set_stream_output_targets()
3794 iris_pack_command(GENX(3DSTATE_SO_BUFFER), so_buffers, sob) { in iris_set_stream_output_targets()
3836 struct GENX(SO_DECL) so_decl[MAX_VERTEX_STREAMS][128]; in iris_create_so_decl_list()
3872 so_decl[stream_id][decls[stream_id]++] = (struct GENX(SO_DECL)) { in iris_create_so_decl_list()
3882 so_decl[stream_id][decls[stream_id]++] = (struct GENX(SO_DECL)) { in iris_create_so_decl_list()
3893 unsigned dwords = GENX(3DSTATE_STREAMOUT_length) + (3 + 2 * max_decls); in iris_create_so_decl_list()
3895 uint32_t *so_decl_map = map + GENX(3DSTATE_STREAMOUT_length); in iris_create_so_decl_list()
3897 iris_pack_command(GENX(3DSTATE_STREAMOUT), map, sol) { in iris_create_so_decl_list()
3922 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST), so_decl_map, list) { in iris_create_so_decl_list()
3935 iris_pack_state(GENX(SO_DECL_ENTRY), so_decl_map + 3 + i * 2, entry) { in iris_create_so_decl_list()
4022 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL) attr_overrides[16] = {}; in iris_emit_sbe_swiz()
4035 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL) *attr = in iris_emit_sbe_swiz()
4112 iris_emit_cmd(batch, GENX(3DSTATE_SBE_SWIZ), sbes) { in iris_emit_sbe_swiz()
4179 iris_emit_cmd(batch, GENX(3DSTATE_SBE), sbe) { in iris_emit_sbe()
4333 uint32_t pkt2[GENX(name##_length)] = {0}; \
4334 _iris_pack_command(batch, GENX(name), pkt2, p) { \
4337 iris_emit_merge(batch, pkt, pkt2, GENX(name##_length)); \
4344 uint32_t pkt2[GENX(name##_length)] = {0}; \
4345 _iris_pack_command(batch, GENX(name), pkt2, p) { \
4349 iris_emit_merge(batch, pkt, pkt2, GENX(name##_length)); \
4364 iris_pack_command(GENX(3DSTATE_VS), shader->derived_data, vs) { in iris_store_vs_state()
4384 iris_pack_command(GENX(3DSTATE_HS), shader->derived_data, hs) { in iris_store_tcs_state()
4429 uint32_t *te_state = ds_state + GENX(3DSTATE_DS_length); in iris_store_tes_state()
4431 iris_pack_command(GENX(3DSTATE_DS), ds_state, ds) { in iris_store_tes_state()
4443 iris_pack_command(GENX(3DSTATE_TE), te_state, te) { in iris_store_tes_state()
4464 iris_pack_command(GENX(3DSTATE_GS), shader->derived_data, gs) { in iris_store_gs_state()
4511 uint32_t *psx_state = ps_state + GENX(3DSTATE_PS_length); in iris_store_fs_state()
4513 iris_pack_command(GENX(3DSTATE_PS), ps_state, ps) { in iris_store_fs_state()
4542 iris_pack_command(GENX(3DSTATE_PS_EXTRA), psx_state, psx) { in iris_store_fs_state()
4571 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA), map, desc) { in iris_store_cs_state()
4602 [IRIS_CACHE_VS] = GENX(3DSTATE_VS_length), in iris_derived_program_state_size()
4603 [IRIS_CACHE_TCS] = GENX(3DSTATE_HS_length), in iris_derived_program_state_size()
4604 [IRIS_CACHE_TES] = GENX(3DSTATE_TE_length) + GENX(3DSTATE_DS_length), in iris_derived_program_state_size()
4605 [IRIS_CACHE_GS] = GENX(3DSTATE_GS_length), in iris_derived_program_state_size()
4607 GENX(3DSTATE_PS_length) + GENX(3DSTATE_PS_EXTRA_length), in iris_derived_program_state_size()
4608 [IRIS_CACHE_CS] = GENX(INTERFACE_DESCRIPTOR_DATA_length), in iris_derived_program_state_size()
5339 iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) { in iris_update_surface_base_address()
5411 iris_load_register_imm32(batch, GENX(GFX_CCS_AUX_INV_num), 1); in genX()
5426 iris_load_register_imm64(batch, GENX(GFX_AUX_TABLE_BASE_ADDR_num), in init_aux_map_state()
5501 iris_emit_cmd(batch, GENX(3DSTATE_CONSTANT_VS), pkt) { in emit_push_constant_packets()
5540 iris_emit_cmd(batch, GENX(3DSTATE_CONSTANT_ALL), pc) { in emit_push_constant_packet_all()
5553 iris_pack_command(GENX(3DSTATE_CONSTANT_ALL), dw, all) { in emit_push_constant_packet_all()
5562 _iris_pack_state(batch, GENX(3DSTATE_CONSTANT_ALL_DATA), in emit_push_constant_packet_all()
5607 iris_emit_reg(batch, GENX(COMMON_SLICE_CHICKEN1), reg) { in genX()
5616 iris_emit_reg(batch, GENX(HIZ_CHICKEN), reg) { in genX()
5652 GENX(CC_VIEWPORT_length), 32, &cc_vp_address); in iris_upload_dirty_render_state()
5663 iris_pack_state(GENX(CC_VIEWPORT), cc_vp_map, ccv) { in iris_upload_dirty_render_state()
5668 cc_vp_map += GENX(CC_VIEWPORT_length); in iris_upload_dirty_render_state()
5671 iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), ptr) { in iris_upload_dirty_render_state()
5683 GENX(SF_CLIP_VIEWPORT_length), 64, &sf_cl_vp_address); in iris_upload_dirty_render_state()
5699 iris_pack_state(GENX(SF_CLIP_VIEWPORT), vp_map, vp) { in iris_upload_dirty_render_state()
5716 vp_map += GENX(SF_CLIP_VIEWPORT_length); in iris_upload_dirty_render_state()
5719 iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), ptr) { in iris_upload_dirty_render_state()
5747 iris_emit_cmd(batch, GENX(3DSTATE_URB_VS), urb) { in iris_upload_dirty_render_state()
5760 const int header_dwords = GENX(BLEND_STATE_length); in iris_upload_dirty_render_state()
5767 MAX2(cso_fb->nr_cbufs, 1) * GENX(BLEND_STATE_ENTRY_length); in iris_upload_dirty_render_state()
5776 iris_pack_state(GENX(BLEND_STATE), &blend_state_header, bs) { in iris_upload_dirty_render_state()
5784 iris_emit_cmd(batch, GENX(3DSTATE_BLEND_STATE_POINTERS), ptr) { in iris_upload_dirty_render_state()
5799 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length), in iris_upload_dirty_render_state()
5801 iris_pack_state(GENX(COLOR_CALC_STATE), cc_map, cc) { in iris_upload_dirty_render_state()
5813 iris_emit_cmd(batch, GENX(3DSTATE_CC_STATE_POINTERS), ptr) { in iris_upload_dirty_render_state()
5885 iris_emit_cmd(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS), ptr) { in iris_upload_dirty_render_state()
5929 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ptr) { in iris_upload_dirty_render_state()
5940 iris_emit_cmd(batch, GENX(3DSTATE_MULTISAMPLE), ms) { in iris_upload_dirty_render_state()
5949 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLE_MASK), ms) { in iris_upload_dirty_render_state()
5972 uint32_t ps_state[GENX(3DSTATE_PS_length)] = {0}; in iris_upload_dirty_render_state()
5973 _iris_pack_command(batch, GENX(3DSTATE_PS), ps_state, ps) { in iris_upload_dirty_render_state()
6014 uint32_t psx_state[GENX(3DSTATE_PS_EXTRA_length)] = {0}; in iris_upload_dirty_render_state()
6015 iris_pack_command(GENX(3DSTATE_PS_EXTRA), psx_state, psx) { in iris_upload_dirty_render_state()
6033 uint32_t *shader_psx = shader_ps + GENX(3DSTATE_PS_length); in iris_upload_dirty_render_state()
6035 GENX(3DSTATE_PS_length)); in iris_upload_dirty_render_state()
6037 GENX(3DSTATE_PS_EXTRA_length)); in iris_upload_dirty_render_state()
6052 iris_emit_cmd(batch, GENX(3DSTATE_HS), hs); in iris_upload_dirty_render_state()
6053 iris_emit_cmd(batch, GENX(3DSTATE_TE), te); in iris_upload_dirty_render_state()
6054 iris_emit_cmd(batch, GENX(3DSTATE_DS), ds); in iris_upload_dirty_render_state()
6056 iris_emit_cmd(batch, GENX(3DSTATE_GS), gs); in iris_upload_dirty_render_state()
6066 const uint32_t dwords = GENX(3DSTATE_SO_BUFFER_length); in iris_upload_dirty_render_state()
6082 STATIC_ASSERT(GENX(3DSTATE_SO_BUFFER_StreamOffset_start) == in iris_upload_dirty_render_state()
6096 ice->state.streamout + GENX(3DSTATE_STREAMOUT_length); in iris_upload_dirty_render_state()
6103 uint32_t dynamic_sol[GENX(3DSTATE_STREAMOUT_length)]; in iris_upload_dirty_render_state()
6104 iris_pack_command(GENX(3DSTATE_STREAMOUT), dynamic_sol, sol) { in iris_upload_dirty_render_state()
6116 GENX(3DSTATE_STREAMOUT_length)); in iris_upload_dirty_render_state()
6120 iris_emit_cmd(batch, GENX(3DSTATE_STREAMOUT), sol); in iris_upload_dirty_render_state()
6134 uint32_t dynamic_clip[GENX(3DSTATE_CLIP_length)]; in iris_upload_dirty_render_state()
6135 iris_pack_command(GENX(3DSTATE_CLIP), &dynamic_clip, cl) { in iris_upload_dirty_render_state()
6162 uint32_t dynamic_sf[GENX(3DSTATE_SF_length)]; in iris_upload_dirty_render_state()
6163 iris_pack_command(GENX(3DSTATE_SF), &dynamic_sf, sf) { in iris_upload_dirty_render_state()
6176 uint32_t dynamic_wm[GENX(3DSTATE_WM_length)]; in iris_upload_dirty_render_state()
6178 iris_pack_command(GENX(3DSTATE_WM), &dynamic_wm, wm) { in iris_upload_dirty_render_state()
6206 uint32_t dynamic_pb[GENX(3DSTATE_PS_BLEND_length)]; in iris_upload_dirty_render_state()
6207 iris_pack_command(GENX(3DSTATE_PS_BLEND), &dynamic_pb, pb) { in iris_upload_dirty_render_state()
6228 uint32_t stencil_refs[GENX(3DSTATE_WM_DEPTH_STENCIL_length)]; in iris_upload_dirty_render_state()
6229 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), &stencil_refs, wmds) { in iris_upload_dirty_render_state()
6252 uint32_t stencil_refs[GENX(3DSTATE_WM_DEPTH_STENCIL_length)]; in iris_upload_dirty_render_state()
6253 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), &stencil_refs, wmds) { in iris_upload_dirty_render_state()
6280 iris_emit_cmd(batch, GENX(3DSTATE_SCISSOR_STATE_POINTERS), ptr) { in iris_upload_dirty_render_state()
6299 GENX(3DSTATE_CLEAR_PARAMS_length); in iris_upload_dirty_render_state()
6301 iris_pack_command(GENX(3DSTATE_CLEAR_PARAMS), clear_params, clear) { in iris_upload_dirty_render_state()
6334 iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) { in iris_upload_dirty_render_state()
6347 iris_emit_cmd(batch, GENX(3DSTATE_VF_TOPOLOGY), topo) { in iris_upload_dirty_render_state()
6365 iris_pack_state(GENX(VERTEX_BUFFER_STATE), state->state, vb) { in iris_upload_dirty_render_state()
6390 iris_pack_state(GENX(VERTEX_BUFFER_STATE), state->state, vb) { in iris_upload_dirty_render_state()
6456 const unsigned vb_dwords = GENX(VERTEX_BUFFER_STATE_length); in iris_upload_dirty_render_state()
6460 _iris_pack_command(batch, GENX(3DSTATE_VERTEX_BUFFERS), map, vb) { in iris_upload_dirty_render_state()
6482 (1 + entries * GENX(VERTEX_ELEMENT_STATE_length))); in iris_upload_dirty_render_state()
6484 uint32_t dynamic_ves[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length)]; in iris_upload_dirty_render_state()
6489 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS), in iris_upload_dirty_render_state()
6492 1 + GENX(VERTEX_ELEMENT_STATE_length) * dyn_count - 2; in iris_upload_dirty_render_state()
6496 GENX(VERTEX_ELEMENT_STATE_length) * sizeof(uint32_t)); in iris_upload_dirty_render_state()
6499 GENX(VERTEX_ELEMENT_STATE_length)]; in iris_upload_dirty_render_state()
6504 iris_pack_state(GENX(VERTEX_ELEMENT_STATE), ve_pack_dest, ve) { in iris_upload_dirty_render_state()
6514 ve_pack_dest += GENX(VERTEX_ELEMENT_STATE_length); in iris_upload_dirty_render_state()
6517 iris_pack_state(GENX(VERTEX_ELEMENT_STATE), ve_pack_dest, ve) { in iris_upload_dirty_render_state()
6528 ve_pack_dest += GENX(VERTEX_ELEMENT_STATE_length); in iris_upload_dirty_render_state()
6531 for (int i = 0; i < GENX(VERTEX_ELEMENT_STATE_length); i++) in iris_upload_dirty_render_state()
6536 (1 + dyn_count * GENX(VERTEX_ELEMENT_STATE_length))); in iris_upload_dirty_render_state()
6541 entries * GENX(3DSTATE_VF_INSTANCING_length)); in iris_upload_dirty_render_state()
6545 uint32_t dynamic_vfi[33 * GENX(3DSTATE_VF_INSTANCING_length)]; in iris_upload_dirty_render_state()
6547 GENX(3DSTATE_VF_INSTANCING_length) * sizeof(uint32_t)); in iris_upload_dirty_render_state()
6550 edgeflag_index * GENX(3DSTATE_VF_INSTANCING_length); in iris_upload_dirty_render_state()
6551 iris_pack_command(GENX(3DSTATE_VF_INSTANCING), vfi_pack_dest, vi) { in iris_upload_dirty_render_state()
6556 for (int i = 0; i < GENX(3DSTATE_VF_INSTANCING_length); i++) in iris_upload_dirty_render_state()
6560 entries * GENX(3DSTATE_VF_INSTANCING_length)); in iris_upload_dirty_render_state()
6569 iris_emit_cmd(batch, GENX(3DSTATE_VF_SGVS), sgv) { in iris_upload_dirty_render_state()
6587 iris_emit_cmd(batch, GENX(3DSTATE_VF), vf) { in iris_upload_dirty_render_state()
6596 iris_emit_cmd(batch, GENX(3DSTATE_VF_STATISTICS), vf) { in iris_upload_dirty_render_state()
6699 uint32_t ib_packet[GENX(3DSTATE_INDEX_BUFFER_length)]; in iris_upload_render_state()
6700 iris_pack_command(GENX(3DSTATE_INDEX_BUFFER), ib_packet, ib) { in iris_upload_render_state()
6793 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { in iris_upload_render_state()
6797 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { in iris_upload_render_state()
6801 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { in iris_upload_render_state()
6806 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { in iris_upload_render_state()
6810 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { in iris_upload_render_state()
6815 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { in iris_upload_render_state()
6819 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in iris_upload_render_state()
6852 iris_emit_cmd(batch, GENX(3DPRIMITIVE), prim) { in iris_upload_render_state()
6887 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { in iris_load_indirect_location()
6891 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { in iris_load_indirect_location()
6895 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { in iris_load_indirect_location()
6921 iris_emit_cmd(batch, GENX(CFE_STATE), cfe) { in iris_upload_compute_walker()
6934 iris_emit_cmd(batch, GENX(COMPUTE_WALKER), cw) { in iris_upload_compute_walker()
6945 cw.InterfaceDescriptor = (struct GENX(INTERFACE_DESCRIPTOR_DATA)) { in iris_upload_compute_walker()
6995 iris_emit_cmd(batch, GENX(MEDIA_VFE_STATE), vfe) { in iris_upload_gpgpu_walker()
7042 iris_emit_cmd(batch, GENX(MEDIA_CURBE_LOAD), curbe) { in iris_upload_gpgpu_walker()
7061 uint32_t desc[GENX(INTERFACE_DESCRIPTOR_DATA_length)]; in iris_upload_gpgpu_walker()
7063 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA), desc, idd) { in iris_upload_gpgpu_walker()
7074 for (int i = 0; i < GENX(INTERFACE_DESCRIPTOR_DATA_length); i++) in iris_upload_gpgpu_walker()
7077 iris_emit_cmd(batch, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), load) { in iris_upload_gpgpu_walker()
7079 GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t); in iris_upload_gpgpu_walker()
7091 iris_emit_cmd(batch, GENX(GPGPU_WALKER), ggw) { in iris_upload_gpgpu_walker()
7104 iris_emit_cmd(batch, GENX(MEDIA_STATE_FLUSH), msf); in iris_upload_gpgpu_walker()
7260 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_start) == 32); in iris_rebind_buffer()
7261 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) == 64); in iris_rebind_buffer()
7284 so_buffers += GENX(3DSTATE_SO_BUFFER_length)) { in iris_rebind_buffer()
7288 STATIC_ASSERT(GENX(3DSTATE_SO_BUFFER_SurfaceBaseAddress_start) == 66); in iris_rebind_buffer()
7289 STATIC_ASSERT(GENX(3DSTATE_SO_BUFFER_SurfaceBaseAddress_bits) == 46); in iris_rebind_buffer()
7842 iris_emit_cmd(batch, GENX(PIPE_CONTROL), pc) { in iris_emit_raw_pipe_control()
7970 iris_emit_cmd(batch, GENX(MI_REPORT_PERF_COUNT), mi_rpc) { in iris_emit_mi_report_perf_count()
8055 iris_emit_reg(batch, GENX(GT_MODE), reg) { in genX()
8182 4 * GENX(RENDER_SURFACE_STATE_length), 64); in genX()