Lines Matching refs:sscreen
135 void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler) in si_init_compiler() argument
140 !sscreen->info.has_dedicated_vram && sscreen->info.chip_class <= GFX8; in si_init_compiler()
143 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) | in si_init_compiler()
144 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) | in si_init_compiler()
148 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options); in si_init_compiler()
155 void si_init_aux_async_compute_ctx(struct si_screen *sscreen) in si_init_aux_async_compute_ctx() argument
157 assert(!sscreen->async_compute_context); in si_init_aux_async_compute_ctx()
158 sscreen->async_compute_context = si_create_context( in si_init_aux_async_compute_ctx()
159 &sscreen->b, in si_init_aux_async_compute_ctx()
161 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) | in si_init_aux_async_compute_ctx()
165 if (sscreen->async_compute_context) in si_init_aux_async_compute_ctx()
166 ((struct si_context*)sscreen->async_compute_context)->cs_max_waves_per_sh = 2; in si_init_aux_async_compute_ctx()
450 struct si_screen *sscreen = (struct si_screen *)screen; in si_create_context() local
454 if (!sscreen->info.has_graphics && !(flags & PIPE_CONTEXT_COMPUTE_ONLY)) in si_create_context()
458 struct radeon_winsys *ws = sscreen->ws; in si_create_context()
465 sctx->has_graphics = sscreen->info.chip_class == GFX6 || !(flags & PIPE_CONTEXT_COMPUTE_ONLY); in si_create_context()
468 sscreen->record_llvm_ir = true; /* racy but not critical */ in si_create_context()
473 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */ in si_create_context()
477 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers); in si_create_context()
478 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers); in si_create_context()
480 sctx->ws = sscreen->ws; in si_create_context()
481 sctx->family = sscreen->info.family; in si_create_context()
482 sctx->chip_class = sscreen->info.chip_class; in si_create_context()
486 &sscreen->b, SI_RESOURCE_FLAG_DRIVER_INTERNAL, in si_create_context()
487 PIPE_USAGE_DEFAULT, 16 * sscreen->info.max_render_backends, 256); in si_create_context()
490 &sscreen->b, PIPE_RESOURCE_FLAG_ENCRYPTED | SI_RESOURCE_FLAG_DRIVER_INTERNAL, in si_create_context()
491 PIPE_USAGE_DEFAULT, 16 * sscreen->info.max_render_backends, 256); in si_create_context()
519 bool smart_access_memory = sscreen->info.smart_access_memory; in si_create_context()
520 bool is_apu = !sscreen->info.has_dedicated_vram; in si_create_context()
539 if (sscreen->info.has_3d_cube_border_color_mipmap) { in si_create_context()
555 sctx->ngg = sscreen->use_ngg; in si_create_context()
640 if (sscreen->info.has_video_hw.uvd_decode || sscreen->info.has_video_hw.vcn_decode || in si_create_context()
641 sscreen->info.has_video_hw.jpeg_decode || sscreen->info.has_video_hw.vce_encode || in si_create_context()
642 sscreen->info.has_video_hw.uvd_encode || sscreen->info.has_video_hw.vcn_encode) { in si_create_context()
657 sscreen->info.tcc_cache_line_size); in si_create_context()
661 if (sscreen->info.has_tmz_support) { in si_create_context()
667 sscreen->info.tcc_cache_line_size); in si_create_context()
716 MAX2(32 * sscreen->info.num_good_compute_units, max_threads_per_block / 64); in si_create_context()
782 struct si_context *saux = (struct si_context *)sscreen->aux_context; in si_create_context()
784 simple_mtx_lock(&sscreen->aux_context_lock); in si_create_context()
790 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL); in si_create_context()
791 sscreen->aux_context->destroy(sscreen->aux_context); in si_create_context()
793 sscreen->aux_context = si_create_context( in si_create_context()
794 &sscreen->b, SI_CONTEXT_FLAG_AUX | in si_create_context()
795 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) | in si_create_context()
796 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY)); in si_create_context()
797 sscreen->aux_context->set_log_context(sscreen->aux_context, aux_log); in si_create_context()
799 simple_mtx_unlock(&sscreen->aux_context_lock); in si_create_context()
801 simple_mtx_lock(&sscreen->async_compute_context_lock); in si_create_context()
802 if (status != PIPE_NO_RESET && sscreen->async_compute_context) { in si_create_context()
803 sscreen->async_compute_context->destroy(sscreen->async_compute_context); in si_create_context()
804 sscreen->async_compute_context = NULL; in si_create_context()
806 simple_mtx_unlock(&sscreen->async_compute_context_lock); in si_create_context()
832 struct si_screen *sscreen = (struct si_screen *)screen; in si_pipe_create_context() local
835 if (sscreen->debug_flags & DBG(CHECK_VM)) in si_pipe_create_context()
840 if (ctx && sscreen->info.chip_class >= GFX9 && sscreen->debug_flags & DBG(SQTT)) { in si_pipe_create_context()
856 if (sscreen->debug_flags & DBG_ALL_SHADERS) in si_pipe_create_context()
862 threaded_context_create(ctx, &sscreen->pool_transfers, in si_pipe_create_context()
865 .create_fence = sscreen->info.is_amdgpu ? in si_pipe_create_context()
883 struct si_screen *sscreen = (struct si_screen *)pscreen; in si_destroy_screen() local
884 struct si_shader_part *parts[] = {sscreen->vs_prologs, sscreen->tcs_epilogs, sscreen->gs_prologs, in si_destroy_screen()
885 sscreen->ps_prologs, sscreen->ps_epilogs}; in si_destroy_screen()
888 if (!sscreen->ws->unref(sscreen->ws)) in si_destroy_screen()
891 if (sscreen->debug_flags & DBG(CACHE_STATS)) { in si_destroy_screen()
892 printf("live shader cache: hits = %u, misses = %u\n", sscreen->live_shader_cache.hits, in si_destroy_screen()
893 sscreen->live_shader_cache.misses); in si_destroy_screen()
894 printf("memory shader cache: hits = %u, misses = %u\n", sscreen->num_memory_shader_cache_hits, in si_destroy_screen()
895 sscreen->num_memory_shader_cache_misses); in si_destroy_screen()
896 printf("disk shader cache: hits = %u, misses = %u\n", sscreen->num_disk_shader_cache_hits, in si_destroy_screen()
897 sscreen->num_disk_shader_cache_misses); in si_destroy_screen()
900 simple_mtx_destroy(&sscreen->aux_context_lock); in si_destroy_screen()
902 if (sscreen->aux_context) { in si_destroy_screen()
903 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log; in si_destroy_screen()
905 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL); in si_destroy_screen()
910 sscreen->aux_context->destroy(sscreen->aux_context); in si_destroy_screen()
913 simple_mtx_destroy(&sscreen->async_compute_context_lock); in si_destroy_screen()
914 if (sscreen->async_compute_context) { in si_destroy_screen()
915 sscreen->async_compute_context->destroy(sscreen->async_compute_context); in si_destroy_screen()
918 util_queue_destroy(&sscreen->shader_compiler_queue); in si_destroy_screen()
919 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority); in si_destroy_screen()
924 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++) in si_destroy_screen()
925 si_destroy_compiler(&sscreen->compiler[i]); in si_destroy_screen()
927 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++) in si_destroy_screen()
928 si_destroy_compiler(&sscreen->compiler_lowp[i]); in si_destroy_screen()
940 simple_mtx_destroy(&sscreen->shader_parts_mutex); in si_destroy_screen()
941 si_destroy_shader_cache(sscreen); in si_destroy_screen()
943 si_destroy_perfcounters(sscreen); in si_destroy_screen()
944 si_gpu_load_kill_thread(sscreen); in si_destroy_screen()
946 simple_mtx_destroy(&sscreen->gpu_load_mutex); in si_destroy_screen()
948 slab_destroy_parent(&sscreen->pool_transfers); in si_destroy_screen()
950 disk_cache_destroy(sscreen->disk_shader_cache); in si_destroy_screen()
951 util_live_shader_cache_deinit(&sscreen->live_shader_cache); in si_destroy_screen()
952 util_idalloc_mt_fini(&sscreen->buffer_ids); in si_destroy_screen()
953 util_vertex_state_cache_deinit(&sscreen->vertex_state_cache); in si_destroy_screen()
955 sscreen->ws->destroy(sscreen->ws); in si_destroy_screen()
956 FREE(sscreen); in si_destroy_screen()
959 static void si_init_gs_info(struct si_screen *sscreen) in si_init_gs_info() argument
961 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class, sscreen->info.family); in si_init_gs_info()
964 static void si_test_vmfault(struct si_screen *sscreen, uint64_t test_flags) in si_test_vmfault() argument
966 struct pipe_context *ctx = sscreen->aux_context; in si_test_vmfault()
968 struct pipe_resource *buf = pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64); in si_test_vmfault()
1022 static void si_disk_cache_create(struct si_screen *sscreen) in si_disk_cache_create() argument
1025 if (sscreen->debug_flags & DBG_ALL_SHADERS) in si_disk_cache_create()
1041 sscreen->disk_shader_cache = disk_cache_create(sscreen->info.name, cache_id, in si_disk_cache_create()
1042 sscreen->info.address32_hi); in si_disk_cache_create()
1047 struct si_screen *sscreen = (struct si_screen *)screen; in si_set_max_shader_compiler_threads() local
1051 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue, max_threads); in si_set_max_shader_compiler_threads()
1066 struct si_screen *sscreen = CALLOC_STRUCT(si_screen); in radeonsi_screen_create_impl() local
1070 if (!sscreen) { in radeonsi_screen_create_impl()
1076 sscreen->options.name = driQueryOptionb(config->options, "radeonsi_" #name); in radeonsi_screen_create_impl()
1080 sscreen->ws = ws; in radeonsi_screen_create_impl()
1081 ws->query_info(ws, &sscreen->info, in radeonsi_screen_create_impl()
1082 sscreen->options.enable_sam, in radeonsi_screen_create_impl()
1083 sscreen->options.disable_sam); in radeonsi_screen_create_impl()
1085 if (sscreen->info.chip_class >= GFX9) { in radeonsi_screen_create_impl()
1086 sscreen->se_tile_repeat = 32 * sscreen->info.max_se; in radeonsi_screen_create_impl()
1088 ac_get_raster_config(&sscreen->info, &sscreen->pa_sc_raster_config, in radeonsi_screen_create_impl()
1089 &sscreen->pa_sc_raster_config_1, &sscreen->se_tile_repeat); in radeonsi_screen_create_impl()
1092 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG", radeonsi_debug_options, 0); in radeonsi_screen_create_impl()
1093 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG", radeonsi_debug_options, 0); in radeonsi_screen_create_impl()
1096 if (sscreen->debug_flags & DBG(NO_GFX)) in radeonsi_screen_create_impl()
1097 sscreen->info.has_graphics = false; in radeonsi_screen_create_impl()
1099 if ((sscreen->debug_flags & DBG(TMZ)) && in radeonsi_screen_create_impl()
1100 !sscreen->info.has_tmz_support) { in radeonsi_screen_create_impl()
1102 FREE(sscreen); in radeonsi_screen_create_impl()
1106 util_idalloc_mt_init_tc(&sscreen->buffer_ids); in radeonsi_screen_create_impl()
1109 sscreen->b.context_create = si_pipe_create_context; in radeonsi_screen_create_impl()
1110 sscreen->b.destroy = si_destroy_screen; in radeonsi_screen_create_impl()
1111 sscreen->b.set_max_shader_compiler_threads = si_set_max_shader_compiler_threads; in radeonsi_screen_create_impl()
1112 sscreen->b.is_parallel_shader_compilation_finished = si_is_parallel_shader_compilation_finished; in radeonsi_screen_create_impl()
1113 sscreen->b.finalize_nir = si_finalize_nir; in radeonsi_screen_create_impl()
1115 si_init_screen_get_functions(sscreen); in radeonsi_screen_create_impl()
1116 si_init_screen_buffer_functions(sscreen); in radeonsi_screen_create_impl()
1117 si_init_screen_fence_functions(sscreen); in radeonsi_screen_create_impl()
1118 si_init_screen_state_functions(sscreen); in radeonsi_screen_create_impl()
1119 si_init_screen_texture_functions(sscreen); in radeonsi_screen_create_impl()
1120 si_init_screen_query_functions(sscreen); in radeonsi_screen_create_impl()
1121 si_init_screen_live_shader_cache(sscreen); in radeonsi_screen_create_impl()
1131 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL); in radeonsi_screen_create_impl()
1133 if (sscreen->debug_flags & DBG(INFO)) in radeonsi_screen_create_impl()
1134 ac_print_gpu_info(&sscreen->info, stdout); in radeonsi_screen_create_impl()
1136 slab_create_parent(&sscreen->pool_transfers, sizeof(struct si_transfer), 64); in radeonsi_screen_create_impl()
1138 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1)); in radeonsi_screen_create_impl()
1139 if (sscreen->force_aniso == -1) { in radeonsi_screen_create_impl()
1140 sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1)); in radeonsi_screen_create_impl()
1143 if (sscreen->force_aniso >= 0) { in radeonsi_screen_create_impl()
1146 1 << util_logbase2(sscreen->force_aniso)); in radeonsi_screen_create_impl()
1149 (void)simple_mtx_init(&sscreen->aux_context_lock, mtx_plain); in radeonsi_screen_create_impl()
1150 (void)simple_mtx_init(&sscreen->async_compute_context_lock, mtx_plain); in radeonsi_screen_create_impl()
1151 (void)simple_mtx_init(&sscreen->gpu_load_mutex, mtx_plain); in radeonsi_screen_create_impl()
1153 si_init_gs_info(sscreen); in radeonsi_screen_create_impl()
1154 if (!si_init_shader_cache(sscreen)) { in radeonsi_screen_create_impl()
1155 FREE(sscreen); in radeonsi_screen_create_impl()
1159 if (sscreen->info.chip_class < GFX10_3) in radeonsi_screen_create_impl()
1160 sscreen->options.vrs2x2 = false; in radeonsi_screen_create_impl()
1162 si_disk_cache_create(sscreen); in radeonsi_screen_create_impl()
1182 num_comp_hi_threads = MIN2(num_comp_hi_threads, ARRAY_SIZE(sscreen->compiler)); in radeonsi_screen_create_impl()
1183 num_comp_lo_threads = MIN2(num_comp_lo_threads, ARRAY_SIZE(sscreen->compiler_lowp)); in radeonsi_screen_create_impl()
1189 &sscreen->shader_compiler_queue, "sh", 64, num_comp_hi_threads, in radeonsi_screen_create_impl()
1191 si_destroy_shader_cache(sscreen); in radeonsi_screen_create_impl()
1192 FREE(sscreen); in radeonsi_screen_create_impl()
1197 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority, "shlo", 64, in radeonsi_screen_create_impl()
1201 si_destroy_shader_cache(sscreen); in radeonsi_screen_create_impl()
1202 FREE(sscreen); in radeonsi_screen_create_impl()
1208 si_init_perfcounters(sscreen); in radeonsi_screen_create_impl()
1210 sscreen->max_memory_usage_kb = sscreen->info.vram_size_kb + sscreen->info.gart_size_kb / 4 * 3; in radeonsi_screen_create_impl()
1213 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 && in radeonsi_screen_create_impl()
1214 sscreen->info.family != CHIP_CARRIZO && in radeonsi_screen_create_impl()
1215 sscreen->info.family != CHIP_STONEY; in radeonsi_screen_create_impl()
1221 if (sscreen->info.chip_class >= GFX10) in radeonsi_screen_create_impl()
1224 else if (sscreen->info.family == CHIP_VEGA12 || sscreen->info.family == CHIP_VEGA20) in radeonsi_screen_create_impl()
1229 unsigned max_offchip_buffers = max_offchip_buffers_per_se * sscreen->info.max_se; in radeonsi_screen_create_impl()
1235 if (sscreen->info.family == CHIP_HAWAII) { in radeonsi_screen_create_impl()
1236 sscreen->tess_offchip_block_dw_size = 4096; in radeonsi_screen_create_impl()
1239 sscreen->tess_offchip_block_dw_size = 8192; in radeonsi_screen_create_impl()
1243 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se; in radeonsi_screen_create_impl()
1244 sscreen->tess_offchip_ring_size = max_offchip_buffers * sscreen->tess_offchip_block_dw_size * 4; in radeonsi_screen_create_impl()
1246 if (sscreen->info.chip_class >= GFX10_3) { in radeonsi_screen_create_impl()
1247 sscreen->vgt_hs_offchip_param = in radeonsi_screen_create_impl()
1250 } else if (sscreen->info.chip_class >= GFX7) { in radeonsi_screen_create_impl()
1251 if (sscreen->info.chip_class >= GFX8) in radeonsi_screen_create_impl()
1253 sscreen->vgt_hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX7(max_offchip_buffers) | in radeonsi_screen_create_impl()
1257 sscreen->vgt_hs_offchip_param = S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers); in radeonsi_screen_create_impl()
1260 sscreen->has_draw_indirect_multi = in radeonsi_screen_create_impl()
1261 (sscreen->info.family >= CHIP_POLARIS10) || in radeonsi_screen_create_impl()
1262 (sscreen->info.chip_class == GFX8 && sscreen->info.pfp_fw_version >= 121 && in radeonsi_screen_create_impl()
1263 sscreen->info.me_fw_version >= 87) || in radeonsi_screen_create_impl()
1264 (sscreen->info.chip_class == GFX7 && sscreen->info.pfp_fw_version >= 211 && in radeonsi_screen_create_impl()
1265 sscreen->info.me_fw_version >= 173) || in radeonsi_screen_create_impl()
1266 (sscreen->info.chip_class == GFX6 && sscreen->info.pfp_fw_version >= 79 && in radeonsi_screen_create_impl()
1267 sscreen->info.me_fw_version >= 142); in radeonsi_screen_create_impl()
1269 sscreen->has_out_of_order_rast = in radeonsi_screen_create_impl()
1270 sscreen->info.has_out_of_order_rast && !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER)); in radeonsi_screen_create_impl()
1271 sscreen->assume_no_z_fights = driQueryOptionb(config->options, "radeonsi_assume_no_z_fights") || in radeonsi_screen_create_impl()
1273 sscreen->commutative_blend_add = in radeonsi_screen_create_impl()
1276 sscreen->allow_draw_out_of_order = driQueryOptionb(config->options, "allow_draw_out_of_order"); in radeonsi_screen_create_impl()
1278 sscreen->use_ngg = !(sscreen->debug_flags & DBG(NO_NGG)) && in radeonsi_screen_create_impl()
1279 sscreen->info.chip_class >= GFX10 && in radeonsi_screen_create_impl()
1280 (sscreen->info.family != CHIP_NAVI14 || in radeonsi_screen_create_impl()
1281 sscreen->info.is_pro_graphics); in radeonsi_screen_create_impl()
1282 sscreen->use_ngg_culling = sscreen->use_ngg && in radeonsi_screen_create_impl()
1283 sscreen->info.max_render_backends >= 2 && in radeonsi_screen_create_impl()
1284 !((sscreen->debug_flags & DBG(NO_NGG_CULLING)) || in radeonsi_screen_create_impl()
1286 sscreen->use_ngg_streamout = false; in radeonsi_screen_create_impl()
1291 if (sscreen->info.chip_class == GFX9) { in radeonsi_screen_create_impl()
1293 sscreen->allow_dcc_msaa_clear_to_reg_for_bpp[bpp_log2] = true; in radeonsi_screen_create_impl()
1299 sscreen->always_allow_dcc_stores = !(sscreen->debug_flags & DBG(NO_DCC_STORE)) && in radeonsi_screen_create_impl()
1300 ((sscreen->info.chip_class >= GFX10_3 && in radeonsi_screen_create_impl()
1301 !sscreen->info.has_dedicated_vram) || in radeonsi_screen_create_impl()
1302 sscreen->debug_flags & DBG(DCC_STORE)); in radeonsi_screen_create_impl()
1304 sscreen->dpbb_allowed = !(sscreen->debug_flags & DBG(NO_DPBB)) && in radeonsi_screen_create_impl()
1305 (sscreen->info.chip_class >= GFX10 || in radeonsi_screen_create_impl()
1307 … (sscreen->info.chip_class == GFX9 && !sscreen->info.has_dedicated_vram) || in radeonsi_screen_create_impl()
1308 sscreen->debug_flags & DBG(DPBB)); in radeonsi_screen_create_impl()
1310 if (sscreen->dpbb_allowed) { in radeonsi_screen_create_impl()
1311 if (sscreen->info.has_dedicated_vram) { in radeonsi_screen_create_impl()
1312 if (sscreen->info.max_render_backends > 4) { in radeonsi_screen_create_impl()
1313 sscreen->pbb_context_states_per_bin = 1; in radeonsi_screen_create_impl()
1314 sscreen->pbb_persistent_states_per_bin = 1; in radeonsi_screen_create_impl()
1316 sscreen->pbb_context_states_per_bin = 3; in radeonsi_screen_create_impl()
1317 sscreen->pbb_persistent_states_per_bin = 8; in radeonsi_screen_create_impl()
1324 sscreen->pbb_context_states_per_bin = sscreen->info.has_gfx9_scissor_bug ? 1 : 6; in radeonsi_screen_create_impl()
1326 sscreen->pbb_persistent_states_per_bin = 16; in radeonsi_screen_create_impl()
1329 assert(sscreen->pbb_context_states_per_bin >= 1 && in radeonsi_screen_create_impl()
1330 sscreen->pbb_context_states_per_bin <= 6); in radeonsi_screen_create_impl()
1331 assert(sscreen->pbb_persistent_states_per_bin >= 1 && in radeonsi_screen_create_impl()
1332 sscreen->pbb_persistent_states_per_bin <= 32); in radeonsi_screen_create_impl()
1335 (void)simple_mtx_init(&sscreen->shader_parts_mutex, mtx_plain); in radeonsi_screen_create_impl()
1336 sscreen->use_monolithic_shaders = (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0; in radeonsi_screen_create_impl()
1338 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE; in radeonsi_screen_create_impl()
1339 if (sscreen->info.chip_class <= GFX8) { in radeonsi_screen_create_impl()
1340 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2; in radeonsi_screen_create_impl()
1341 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2; in radeonsi_screen_create_impl()
1345 sscreen->debug_flags |= DBG_ALL_SHADERS; in radeonsi_screen_create_impl()
1361 if (sscreen->info.has_eqaa_surface_allocator) { in radeonsi_screen_create_impl()
1366 sscreen->eqaa_force_coverage_samples = s; in radeonsi_screen_create_impl()
1367 sscreen->eqaa_force_z_samples = z; in radeonsi_screen_create_impl()
1368 sscreen->eqaa_force_color_samples = f; in radeonsi_screen_create_impl()
1372 sscreen->ngg_subgroup_size = 128; in radeonsi_screen_create_impl()
1373 sscreen->ge_wave_size = 64; in radeonsi_screen_create_impl()
1374 sscreen->ps_wave_size = 64; in radeonsi_screen_create_impl()
1375 sscreen->compute_wave_size = 64; in radeonsi_screen_create_impl()
1377 if (sscreen->info.chip_class >= GFX10) { in radeonsi_screen_create_impl()
1387 if (sscreen->debug_flags & DBG(W32_GE)) in radeonsi_screen_create_impl()
1388 sscreen->ge_wave_size = 32; in radeonsi_screen_create_impl()
1389 if (sscreen->debug_flags & DBG(W32_PS)) in radeonsi_screen_create_impl()
1390 sscreen->ps_wave_size = 32; in radeonsi_screen_create_impl()
1391 if (sscreen->debug_flags & DBG(W32_CS)) in radeonsi_screen_create_impl()
1392 sscreen->compute_wave_size = 32; in radeonsi_screen_create_impl()
1394 if (sscreen->debug_flags & DBG(W64_GE)) in radeonsi_screen_create_impl()
1395 sscreen->ge_wave_size = 64; in radeonsi_screen_create_impl()
1396 if (sscreen->debug_flags & DBG(W64_PS)) in radeonsi_screen_create_impl()
1397 sscreen->ps_wave_size = 64; in radeonsi_screen_create_impl()
1398 if (sscreen->debug_flags & DBG(W64_CS)) in radeonsi_screen_create_impl()
1399 sscreen->compute_wave_size = 64; in radeonsi_screen_create_impl()
1403 sscreen->aux_context = si_create_context( in radeonsi_screen_create_impl()
1404 &sscreen->b, in radeonsi_screen_create_impl()
1406 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) | in radeonsi_screen_create_impl()
1407 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY)); in radeonsi_screen_create_impl()
1409 if (sscreen->options.aux_debug) { in radeonsi_screen_create_impl()
1412 sscreen->aux_context->set_log_context(sscreen->aux_context, log); in radeonsi_screen_create_impl()
1416 si_test_blit(sscreen); in radeonsi_screen_create_impl()
1419 si_test_dma_perf(sscreen); in radeonsi_screen_create_impl()
1423 si_test_vmfault(sscreen, test_flags); in radeonsi_screen_create_impl()
1426 si_test_gds((struct si_context *)sscreen->aux_context); in radeonsi_screen_create_impl()
1429 si_test_gds_memory_management((struct si_context *)sscreen->aux_context, 32 * 1024, 4, in radeonsi_screen_create_impl()
1433 si_test_gds_memory_management((struct si_context *)sscreen->aux_context, 4, 1, in radeonsi_screen_create_impl()
1437 ac_print_shadowed_regs(&sscreen->info); in radeonsi_screen_create_impl()
1440 return &sscreen->b; in radeonsi_screen_create_impl()