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Lines Matching refs:sscreen

45 static enum radeon_surf_mode si_choose_tiling(struct si_screen *sscreen,
121 static unsigned si_texture_get_offset(struct si_screen *sscreen, struct si_texture *tex, in si_texture_get_offset() argument
125 if (sscreen->info.chip_class >= GFX9) { in si_texture_get_offset()
157 static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surface, in si_init_surface() argument
181 if ((sscreen->debug_flags & DBG(NO_HYPERZ)) || in si_init_surface()
185 (sscreen->info.chip_class >= GFX9 || array_mode == RADEON_SURF_MODE_2D)) { in si_init_surface()
191 if (sscreen->info.chip_class == GFX8) in si_init_surface()
202 if (sscreen->info.chip_class >= GFX8) { in si_init_surface()
207 if (ptex->nr_samples >= 2 && sscreen->debug_flags & DBG(NO_DCC_MSAA)) in si_init_surface()
214 (sscreen->debug_flags & DBG(NO_DCC) || in si_init_surface()
215 (ptex->bind & PIPE_BIND_SCANOUT && sscreen->debug_flags & DBG(NO_DISPLAY_DCC)))) in si_init_surface()
219 if (sscreen->info.chip_class < GFX10_3 && in si_init_surface()
223 switch (sscreen->info.chip_class) { in si_init_surface()
226 if (sscreen->info.family == CHIP_STONEY && bpe == 16 && ptex->nr_samples >= 2) in si_init_surface()
240 if (sscreen->info.family == CHIP_RAVEN && ptex->nr_storage_samples >= 2 && bpe < 4) in si_init_surface()
268 if (sscreen->debug_flags & DBG(NO_FMASK)) in si_init_surface()
271 if (sscreen->info.chip_class == GFX9 && (ptex->flags & SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE)) { in si_init_surface()
279 if (sscreen->info.chip_class >= GFX10) in si_init_surface()
285 r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe, array_mode, surface); in si_init_surface()
296 struct si_screen *sscreen = sctx->screen; in si_eliminate_fast_color_clear() local
299 if (ctx == sscreen->aux_context) in si_eliminate_fast_color_clear()
300 simple_mtx_lock(&sscreen->aux_context_lock); in si_eliminate_fast_color_clear()
315 if (ctx == sscreen->aux_context) in si_eliminate_fast_color_clear()
316 simple_mtx_unlock(&sscreen->aux_context_lock); in si_eliminate_fast_color_clear()
319 void si_texture_discard_cmask(struct si_screen *sscreen, struct si_texture *tex) in si_texture_discard_cmask() argument
338 p_atomic_inc(&sscreen->dirty_tex_counter); in si_texture_discard_cmask()
339 p_atomic_inc(&sscreen->compressed_colortex_counter); in si_texture_discard_cmask()
352 static bool si_texture_discard_dcc(struct si_screen *sscreen, struct si_texture *tex) in si_texture_discard_dcc() argument
361 p_atomic_inc(&sscreen->dirty_tex_counter); in si_texture_discard_dcc()
388 struct si_screen *sscreen = sctx->screen; in si_texture_disable_dcc() local
391 return si_texture_discard_dcc(sscreen, tex); in si_texture_disable_dcc()
396 if (&sctx->b == sscreen->aux_context) in si_texture_disable_dcc()
397 simple_mtx_lock(&sscreen->aux_context_lock); in si_texture_disable_dcc()
403 if (&sctx->b == sscreen->aux_context) in si_texture_disable_dcc()
404 simple_mtx_unlock(&sscreen->aux_context_lock); in si_texture_disable_dcc()
406 return si_texture_discard_dcc(sscreen, tex); in si_texture_disable_dcc()
512 static void si_set_tex_bo_metadata(struct si_screen *sscreen, struct si_texture *tex) in si_set_tex_bo_metadata() argument
526 sscreen->make_texture_descriptor(sscreen, tex, true, res->target, res->format, swizzle, 0, in si_set_tex_bo_metadata()
529 si_set_mutable_tex_desc_fields(sscreen, tex, &tex->surface.u.legacy.level[0], 0, 0, in si_set_tex_bo_metadata()
532 ac_surface_get_umd_metadata(&sscreen->info, &tex->surface, in si_set_tex_bo_metadata()
535 sscreen->ws->buffer_set_metadata(sscreen->ws, tex->buffer.buf, &md, &tex->surface); in si_set_tex_bo_metadata()
540 struct si_screen *sscreen = (struct si_screen *)tex->buffer.b.b.screen; in si_displayable_dcc_needs_explicit_flush() local
542 if (sscreen->info.chip_class <= GFX8) in si_displayable_dcc_needs_explicit_flush()
564 struct si_screen *sscreen = (struct si_screen *)screen; in si_resource_get_param() local
582 *value = ac_surface_get_plane_stride(sscreen->info.chip_class, in si_resource_get_param()
590 *value = ac_surface_get_plane_offset(sscreen->info.chip_class, in si_resource_get_param()
641 struct si_screen *sscreen = (struct si_screen *)screen; in si_texture_get_handle() local
651 sctx = (struct si_context *)(ctx ? ctx : sscreen->aux_context); in si_texture_get_handle()
672 whandle->offset = ac_surface_get_plane_offset(sscreen->info.chip_class, in si_texture_get_handle()
674 whandle->stride = ac_surface_get_plane_stride(sscreen->info.chip_class, in si_texture_get_handle()
677 return sscreen->ws->buffer_get_handle(sscreen->ws, res->buf, whandle); in si_texture_get_handle()
681 if (sscreen->ws->buffer_is_suballocated(res->buf) || tex->surface.tile_swizzle || in si_texture_get_handle()
683 sscreen->info.has_local_buffers)) { in si_texture_get_handle()
721 si_texture_discard_cmask(sscreen, tex); in si_texture_get_handle()
726 si_set_tex_bo_metadata(sscreen, tex); in si_texture_get_handle()
728 if (sscreen->info.chip_class >= GFX9) { in si_texture_get_handle()
738 if (sscreen->ws->buffer_is_suballocated(res->buf) || in si_texture_get_handle()
741 sscreen->info.has_local_buffers)) { in si_texture_get_handle()
790 return sscreen->ws->buffer_get_handle(sscreen->ws, res->buf, whandle); in si_texture_get_handle()
793 void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex, in si_print_texture_info() argument
818 ac_surface_print_info(f, &sscreen->info, &tex->surface); in si_print_texture_info()
823 if (sscreen->info.chip_class >= GFX9) { in si_print_texture_info()
889 struct si_screen *sscreen = (struct si_screen *)screen; in si_texture_create_object() local
891 if (!sscreen->info.has_3d_cube_border_color_mipmap && in si_texture_create_object()
924 tex->tc_compatible_htile = (sscreen->info.chip_class == GFX8 && in si_texture_create_object()
927 (sscreen->info.chip_class >= GFX8 && in si_texture_create_object()
935 if (sscreen->info.chip_class >= GFX9 && base->format == PIPE_FORMAT_Z16_UNORM) in si_texture_create_object()
949 if (!ac_surface_override_offset_stride(&sscreen->info, &tex->surface, in si_texture_create_object()
957 if (sscreen->info.chip_class >= GFX9) { in si_texture_create_object()
963 if (sscreen->info.chip_class == GFX10 && base->last_level > 0) in si_texture_create_object()
974 if (sscreen->info.chip_class == GFX8 && in si_texture_create_object()
995 radeon_bo_reference(sscreen->ws, &resource->buf, plane0->buffer.buf); in si_texture_create_object()
999 si_init_resource_fields(sscreen, resource, alloc_size, alignment); in si_texture_create_object()
1001 if (!si_alloc_resource(sscreen, resource)) in si_texture_create_object()
1005 resource->gpu_address = sscreen->ws->buffer_get_virtual_address(resource->buf); in si_texture_create_object()
1008 resource->domains = sscreen->ws->buffer_get_initial_domain(resource->buf); in si_texture_create_object()
1010 if (sscreen->ws->buffer_get_flags) in si_texture_create_object()
1011 resource->flags = sscreen->ws->buffer_get_flags(resource->buf); in si_texture_create_object()
1028 if (sscreen->info.chip_class >= GFX9 || tex->tc_compatible_htile) in si_texture_create_object()
1049 } else if (sscreen->info.chip_class >= GFX9) { in si_texture_create_object()
1100 simple_mtx_lock(&sscreen->aux_context_lock); in si_texture_create_object()
1101 si_execute_clears((struct si_context *)sscreen->aux_context, in si_texture_create_object()
1103 sscreen->aux_context->flush(sscreen->aux_context, NULL, 0); in si_texture_create_object()
1104 simple_mtx_unlock(&sscreen->aux_context_lock); in si_texture_create_object()
1110 if (sscreen->debug_flags & DBG(VM)) { in si_texture_create_object()
1119 if (sscreen->debug_flags & DBG(TEX)) { in si_texture_create_object()
1123 si_print_texture_info(sscreen, tex, &log); in si_texture_create_object()
1136 static enum radeon_surf_mode si_choose_tiling(struct si_screen *sscreen, in si_choose_tiling() argument
1156 if (sscreen->info.chip_class == GFX8 && tc_compatible_htile) in si_choose_tiling()
1163 if (sscreen->debug_flags & DBG(NO_TILING) || in si_choose_tiling()
1164 (templ->bind & PIPE_BIND_SCANOUT && sscreen->debug_flags & DBG(NO_DISPLAY_TILING))) in si_choose_tiling()
1192 if (templ->width0 <= 16 || templ->height0 <= 16 || (sscreen->debug_flags & DBG(NO_2D_TILING))) in si_choose_tiling()
1204 struct si_screen *sscreen = (struct si_screen *)screen; in si_texture_create_with_modifier() local
1212 if (is_zs && sscreen->eqaa_force_z_samples) { in si_texture_create_with_modifier()
1214 ((struct pipe_resource *)templ)->nr_storage_samples = sscreen->eqaa_force_z_samples; in si_texture_create_with_modifier()
1215 } else if (!is_zs && sscreen->eqaa_force_color_samples) { in si_texture_create_with_modifier()
1216 ((struct pipe_resource *)templ)->nr_samples = sscreen->eqaa_force_coverage_samples; in si_texture_create_with_modifier()
1217 ((struct pipe_resource *)templ)->nr_storage_samples = sscreen->eqaa_force_color_samples; in si_texture_create_with_modifier()
1224 sscreen->info.chip_class >= GFX8 && in si_texture_create_with_modifier()
1230 sscreen->info.family != CHIP_TONGA && sscreen->info.family != CHIP_ICELAND && in si_texture_create_with_modifier()
1232 !(sscreen->debug_flags & DBG(NO_HYPERZ)) && !is_flushed_depth && in si_texture_create_with_modifier()
1235 enum radeon_surf_mode tile_mode = si_choose_tiling(sscreen, templ, tc_compatible_htile); in si_texture_create_with_modifier()
1264 if (si_init_surface(sscreen, &surface[i], &plane_templ[i], tile_mode, modifier, in si_texture_create_with_modifier()
1312 struct si_screen *sscreen = (struct si_screen *)screen; in si_query_dmabuf_modifiers() local
1315 ac_get_supported_modifiers(&sscreen->info, &(struct ac_modifier_options) { in si_query_dmabuf_modifiers()
1316 .dcc = !(sscreen->debug_flags & DBG(NO_DCC)), in si_query_dmabuf_modifiers()
1320 .dcc_retile = !(sscreen->debug_flags & DBG(NO_DCC)), in si_query_dmabuf_modifiers()
1392 struct si_screen *sscreen = (struct si_screen *)screen; in si_modifier_supports_resource() local
1395 ac_modifier_max_extent(&sscreen->info, modifier, &max_width, &max_height); in si_modifier_supports_resource()
1450 static struct pipe_resource *si_texture_from_winsys_buffer(struct si_screen *sscreen, in si_texture_from_winsys_buffer() argument
1466 sscreen->ws->buffer_get_metadata(sscreen->ws, buf, &metadata, &surface); in si_texture_from_winsys_buffer()
1493 r = si_init_surface(sscreen, &surface, templ, metadata.mode, modifier, true, in si_texture_from_winsys_buffer()
1498 tex = si_texture_create_object(&sscreen->b, templ, &surface, NULL, buf, in si_texture_from_winsys_buffer()
1523 ptex->offset != ac_surface_get_plane_offset(sscreen->info.chip_class, in si_texture_from_winsys_buffer()
1525 ptex->stride != ac_surface_get_plane_stride(sscreen->info.chip_class, in si_texture_from_winsys_buffer()
1539 if (!ac_surface_set_umd_metadata(&sscreen->info, &tex->surface, in si_texture_from_winsys_buffer()
1548 if (ac_surface_get_plane_offset(sscreen->info.chip_class, &tex->surface, 0, 0) + in si_texture_from_winsys_buffer()
1559 if (si_texture_discard_dcc(sscreen, tex)) { in si_texture_from_winsys_buffer()
1561 si_set_tex_bo_metadata(sscreen, tex); in si_texture_from_winsys_buffer()
1573 struct si_screen *sscreen = (struct si_screen *)screen; in si_texture_from_handle() local
1582 buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle, sscreen->info.max_alignment); in si_texture_from_handle()
1601 return si_texture_from_winsys_buffer(sscreen, templ, buf, whandle->stride, whandle->offset, in si_texture_from_handle()
1707 static bool si_can_invalidate_texture(struct si_screen *sscreen, struct si_texture *tex, in si_can_invalidate_texture() argument
1718 struct si_screen *sscreen = sctx->screen; in si_texture_invalidate_storage() local
1725 si_alloc_resource(sscreen, &tex->buffer); in si_texture_invalidate_storage()
1730 p_atomic_inc(&sscreen->dirty_tex_counter); in si_texture_invalidate_storage()
1917 bool vi_dcc_formats_compatible(struct si_screen *sscreen, enum pipe_format format1, in vi_dcc_formats_compatible() argument
1957 if (vi_alpha_is_on_msb(sscreen, format1) != vi_alpha_is_on_msb(sscreen, format2)) in vi_dcc_formats_compatible()
2123 struct si_screen *sscreen = (struct si_screen *)screen; in si_memobj_from_handle() local
2130 buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle, sscreen->info.max_alignment); in si_memobj_from_handle()
2156 struct si_screen *sscreen = (struct si_screen *)screen; in si_resource_from_memobj() local
2164 res = si_texture_from_winsys_buffer(sscreen, templ, memobj->buf, in si_resource_from_memobj()
2177 radeon_bo_reference(sscreen->ws, &buf, memobj->buf); in si_resource_from_memobj()
2200 void si_init_screen_texture_functions(struct si_screen *sscreen) in si_init_screen_texture_functions() argument
2202 sscreen->b.resource_from_handle = si_texture_from_handle; in si_init_screen_texture_functions()
2203 sscreen->b.resource_get_handle = si_texture_get_handle; in si_init_screen_texture_functions()
2204 sscreen->b.resource_get_param = si_resource_get_param; in si_init_screen_texture_functions()
2205 sscreen->b.resource_get_info = si_texture_get_info; in si_init_screen_texture_functions()
2206 sscreen->b.resource_from_memobj = si_resource_from_memobj; in si_init_screen_texture_functions()
2207 sscreen->b.memobj_create_from_handle = si_memobj_from_handle; in si_init_screen_texture_functions()
2208 sscreen->b.memobj_destroy = si_memobj_destroy; in si_init_screen_texture_functions()
2209 sscreen->b.check_resource_capability = si_check_resource_capability; in si_init_screen_texture_functions()
2215 if (sscreen->info.chip_class >= GFX9 && sscreen->info.kernel_has_modifiers) { in si_init_screen_texture_functions()
2216 sscreen->b.resource_create_with_modifiers = si_texture_create_with_modifiers; in si_init_screen_texture_functions()
2217 sscreen->b.query_dmabuf_modifiers = si_query_dmabuf_modifiers; in si_init_screen_texture_functions()
2218 sscreen->b.is_dmabuf_modifier_supported = si_is_dmabuf_modifier_supported; in si_init_screen_texture_functions()
2219 sscreen->b.get_dmabuf_modifier_planes = si_get_dmabuf_modifier_planes; in si_init_screen_texture_functions()