89       unsigned size = GENX(SLICE_HASH_TABLE_length) * 4;  in genX()
95       struct GENX(SLICE_HASH_TABLE) table;  in genX()
98       GENX(SLICE_HASH_TABLE_pack)(NULL, device->slice_hash.map, &table);  in genX()
101    anv_batch_emit(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) {  in genX()
106    anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) {  in genX()
130    anv_batch_emit(batch, GENX(3DSTATE_SUBSLICE_HASH_TABLE), p) {  in genX()
148    anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), p) {  in genX()
165    anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {  in init_render_queue_state()
174    anv_batch_write_reg(&batch, GENX(CACHE_MODE_1), cm1) {  in init_render_queue_state()
184    anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);  in init_render_queue_state()
186    anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {  in init_render_queue_state()
196    anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck);  in init_render_queue_state()
208    anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp);  in init_render_queue_state()
217    anv_batch_write_reg(&batch, GENX(SAMPLER_MODE), sm) {  in init_render_queue_state()
225    anv_batch_write_reg(&batch, GENX(HALF_SLICE_CHICKEN7), hsc7) {  in init_render_queue_state()
230    anv_batch_write_reg(&batch, GENX(TCCNTLREG), tcc) {  in init_render_queue_state()
244       anv_batch_write_reg(&batch, GENX(CACHE_MODE_0), cm0) {  in init_render_queue_state()
255    anv_batch_write_reg(&batch, GENX(CS_CHICKEN1), cc1) {  in init_render_queue_state()
261 #define AA_LINE_QUALITY_REG GENX(3D_CHICKEN3)  in init_render_queue_state()
263 #define AA_LINE_QUALITY_REG GENX(CHICKEN_RASTER_1)  in init_render_queue_state()
279       anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {  in init_render_queue_state()
280          lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num);  in init_render_queue_state()
283       anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {  in init_render_queue_state()
284          lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num) + 4;  in init_render_queue_state()
297       anv_batch_write_reg(&batch, GENX(CS_DEBUG_MODE2), csdm2) {  in init_render_queue_state()
302       anv_batch_write_reg(&batch, GENX(INSTPM), instpm) {  in init_render_queue_state()
318    anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);  in init_render_queue_state()
364 #define L3_ALLOCATION_REG GENX(L3ALLOC)  in genX()
365 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)  in genX()
367 #define L3_ALLOCATION_REG GENX(L3CNTLREG)  in genX()
368 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)  in genX()
424    anv_batch_write_reg(batch, GENX(L3SQCREG1), l3sqc) {  in genX()
438    anv_batch_write_reg(batch, GENX(L3CNTLREG2), l3cr2) {  in genX()
449    anv_batch_write_reg(batch, GENX(L3CNTLREG3), l3cr3) {  in genX()
463       anv_batch_write_reg(batch, GENX(SCRATCH1), s1) {  in genX()
466       anv_batch_write_reg(batch, GENX(CHICKEN3), c3) {  in genX()
480    anv_batch_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) {  in genX()
540    anv_batch_emit(batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) {  in genX()
605    anv_batch_emit(batch, GENX(3DSTATE_CPS), cps) {  in genX()
615          cps_states.map + GENX(CPS_STATE_length) * 4 * i;  in genX()
616       struct GENX(CPS_STATE) cps_state = {  in genX()
625       GENX(CPS_STATE_pack)(NULL, cps_state_dwords, &cps_state);  in genX()
628    anv_batch_emit(batch, GENX(3DSTATE_CPS_POINTERS), cps) {  in genX()
826       struct GENX(SAMPLER_STATE) sampler_state = {  in genX()
884       GENX(SAMPLER_STATE_pack)(NULL, sampler->state[p], &sampler_state);  in genX()
888                 sampler->state[p], GENX(SAMPLER_STATE_length) * 4);  in genX()