129                      midgard_reg_mode reg_mode)  in validate_expand_mode()  argument
136                 assert(reg_mode == midgard_reg_mode_8 ||  in validate_expand_mode()
137                        reg_mode == midgard_reg_mode_16);  in validate_expand_mode()
141                 assert(reg_mode == midgard_reg_mode_8 ||  in validate_expand_mode()
142                        reg_mode == midgard_reg_mode_16);  in validate_expand_mode()
146                 assert(reg_mode == midgard_reg_mode_8 ||  in validate_expand_mode()
147                        reg_mode == midgard_reg_mode_16);  in validate_expand_mode()
151                 assert(reg_mode != midgard_reg_mode_8);  in validate_expand_mode()
155                 assert(reg_mode != midgard_reg_mode_8);  in validate_expand_mode()
159                 assert(reg_mode == midgard_reg_mode_16);  in validate_expand_mode()
163                 assert(reg_mode == midgard_reg_mode_16);  in validate_expand_mode()
404                        midgard_reg_mode reg_mode,  in print_vec_selectors_64()  argument
436                     midgard_reg_mode reg_mode,  in print_vec_selectors()  argument
440         assert(reg_mode != midgard_reg_mode_64);  in print_vec_selectors()
442         unsigned mask_skip = MAX2(bits_for_mode(reg_mode) / 16, 1);  in print_vec_selectors()
444         bool is_vec16 = reg_mode == midgard_reg_mode_8;  in print_vec_selectors()
556         unsigned bits = bits_for_mode_halved(alu->reg_mode, expands);  in print_vector_constants()
633                 mir_print_constant_component(fp, consts, c, alu->reg_mode,  in print_vector_constants()
818         midgard_reg_mode mode = alu_field->reg_mode;  in print_vector_field()