Lines Matching refs:ins
186 midgard_instruction ins = { in v_branch() local
198 return ins; in v_branch()
202 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name) in attach_constants() argument
204 ins->has_constants = true; in attach_constants()
205 memcpy(&ins->constants, constants, 16); in attach_constants()
474 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to); in emit_explicit_constant() local
475 attach_constants(ctx, &ins, constant_value, node + 1); in emit_explicit_constant()
476 emit_mir_instruction(ctx, ins); in emit_explicit_constant()
504 midgard_instruction ins = emit_image_op(ctx, instr, true); \
505 emit_atomic(ctx, instr, false, midgard_op_atomic_##op, ins.dest); \
596 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bo… in mir_copy_src() argument
627 ins->src[to] = nir_src_index(NULL, &src.src); in mir_copy_src()
628 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits; in mir_copy_src()
631 ins->swizzle[to][c] = src.swizzle[ in mir_copy_src()
951 midgard_instruction ins = { in emit_alu() local
960 &ins.roundmode : NULL; in emit_alu()
962 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i) in emit_alu()
963 ins.src[i] = ~0; in emit_alu()
966 ins.src[0] = ~0; in emit_alu()
967 …mir_copy_src(&ins, instr, 0, 1, &ins.src_abs[1], &ins.src_neg[1], &ins.src_invert[1], roundptr, is… in emit_alu()
988 …mir_copy_src(&ins, instr, i, to, &ins.src_abs[to], &ins.src_neg[to], &ins.src_invert[to], roundptr… in emit_alu()
991 if (instr->op == nir_op_b32csel && ins.src_invert[2]) { in emit_alu()
992 ins.src_invert[2] = false; in emit_alu()
1001 ins.src_neg[1] ^= true; in emit_alu()
1004 ins.src_abs[1] = true; in emit_alu()
1007 ins.mask = mask_of(nr_components); in emit_alu()
1014 ins.mask &= instr->dest.write_mask; in emit_alu()
1016 ins.op = op; in emit_alu()
1017 ins.outmod = outmod; in emit_alu()
1027 ins.has_inline_constant = false; in emit_alu()
1028 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); in emit_alu()
1029 ins.src_types[1] = nir_type_float32; in emit_alu()
1030 ins.has_constants = true; in emit_alu()
1033 ins.constants.f32[0] = 1.0f; in emit_alu()
1035 ins.constants.i32[0] = 1; in emit_alu()
1038 ins.swizzle[1][c] = 0; in emit_alu()
1040 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); in emit_alu()
1041 ins.src_types[1] = nir_type_float16; in emit_alu()
1042 ins.has_constants = true; in emit_alu()
1043 ins.constants.i16[0] = _mesa_float_to_half(1.0); in emit_alu()
1046 ins.swizzle[1][c] = 0; in emit_alu()
1049 ins.has_inline_constant = false; in emit_alu()
1050 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); in emit_alu()
1051 ins.src_types[1] = ins.src_types[0]; in emit_alu()
1052 ins.has_constants = true; in emit_alu()
1053 ins.constants.u32[0] = 0; in emit_alu()
1056 ins.swizzle[1][c] = 0; in emit_alu()
1058 ins.dest_type = nir_type_uint16; in emit_alu()
1059 ins.mask = mask_of(nr_components * 2); in emit_alu()
1060 ins.is_pack = true; in emit_alu()
1062 ins.dest_type = nir_type_uint8; in emit_alu()
1063 ins.mask = mask_of(nr_components * 4); in emit_alu()
1064 ins.is_pack = true; in emit_alu()
1066 ins.dest_type = nir_type_uint32; in emit_alu()
1067 ins.mask = mask_of(nr_components >> 1); in emit_alu()
1068 ins.is_pack = true; in emit_alu()
1070 ins.dest_type = nir_type_uint32; in emit_alu()
1071 ins.mask = mask_of(nr_components >> 2); in emit_alu()
1072 ins.is_pack = true; in emit_alu()
1080 unsigned orig_mask = ins.mask; in emit_alu()
1083 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back)); in emit_alu()
1092 ins.mask = 1 << i; in emit_alu()
1093 ins.mask &= orig_mask; in emit_alu()
1097 ins_split[j].mask |= ins.mask; in emit_alu()
1098 ins.mask = 0; in emit_alu()
1103 if (!ins.mask) in emit_alu()
1107 … ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */ in emit_alu()
1109 ins_split[ins_count] = ins; in emit_alu()
1118 emit_mir_instruction(ctx, ins); in emit_alu()
1125 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read) in mir_set_intr_mask() argument
1141 ins->dest_type = nir_type_uint | dsize; in mir_set_intr_mask()
1142 mir_set_bytemask(ins, bytemask); in mir_set_intr_mask()
1159 midgard_instruction ins; in emit_ubo_read() local
1168 ins = m_ld_ubo_32(dest, 0); in emit_ubo_read()
1170 ins = m_ld_ubo_64(dest, 0); in emit_ubo_read()
1172 ins = m_ld_ubo_128(dest, 0); in emit_ubo_read()
1176 ins.constants.u32[0] = offset; in emit_ubo_read()
1179 mir_set_intr_mask(instr, &ins, true); in emit_ubo_read()
1182 ins.src[2] = nir_src_index(ctx, indirect_offset); in emit_ubo_read()
1183 ins.src_types[2] = nir_type_uint32; in emit_ubo_read()
1184 ins.load_store.index_shift = indirect_shift; in emit_ubo_read()
1188 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[2]); ++i) in emit_ubo_read()
1189 ins.swizzle[2][i] = 0; in emit_ubo_read()
1191 ins.load_store.index_reg = REGISTER_LDST_ZERO; in emit_ubo_read()
1195 mir_set_ubo_offset(&ins, indirect_offset, offset); in emit_ubo_read()
1197 midgard_pack_ubo_index_imm(&ins.load_store, index); in emit_ubo_read()
1199 return emit_mir_instruction(ctx, ins); in emit_ubo_read()
1214 midgard_instruction ins; in emit_global() local
1222 ins = m_ld_32(srcdest, 0); in emit_global()
1224 ins = m_ld_64(srcdest, 0); in emit_global()
1226 ins = m_ld_128(srcdest, 0); in emit_global()
1234 ins = m_st_32(srcdest, 0); in emit_global()
1236 ins = m_st_64(srcdest, 0); in emit_global()
1238 ins = m_st_128(srcdest, 0); in emit_global()
1243 mir_set_offset(ctx, &ins, offset, seg); in emit_global()
1244 mir_set_intr_mask(instr, &ins, is_read); in emit_global()
1247 assert(ins.mask); in emit_global()
1248 unsigned first_component = __builtin_ffs(ins.mask) - 1; in emit_global()
1250 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i) { in emit_global()
1251 if (!(ins.mask & (1 << i))) in emit_global()
1252 ins.swizzle[0][i] = first_component; in emit_global()
1255 emit_mir_instruction(ctx, ins); in emit_global()
1282 midgard_instruction ins = { in emit_atomic() local
1298 ins.src[2] = val; in emit_atomic()
1299 ins.src_types[2] = type | bitsize; in emit_atomic()
1300 ins.src[3] = xchg_val; in emit_atomic()
1303 ins.load_store.arg_reg = REGISTER_LDST_LOCAL_STORAGE_PTR; in emit_atomic()
1304 ins.load_store.arg_comp = COMPONENT_Z; in emit_atomic()
1305 ins.load_store.bitsize_toggle = true; in emit_atomic()
1308 ins.swizzle[1][i] = i; in emit_atomic()
1310 ins.src[1] = is_image ? image_direct_address : in emit_atomic()
1312 ins.src_types[1] = nir_type_uint64; in emit_atomic()
1316 ins.swizzle[2][i] = i; in emit_atomic()
1318 ins.src[2] = image_direct_address; in emit_atomic()
1319 ins.src_types[2] = nir_type_uint64; in emit_atomic()
1321 ins.load_store.arg_reg = REGISTER_LDST_ZERO; in emit_atomic()
1322 ins.load_store.bitsize_toggle = true; in emit_atomic()
1323 ins.load_store.index_format = midgard_index_address_u64; in emit_atomic()
1325 mir_set_offset(ctx, &ins, src_offset, is_shared ? LDST_SHARED : LDST_GLOBAL); in emit_atomic()
1327 mir_set_intr_mask(&instr->instr, &ins, true); in emit_atomic()
1329 emit_mir_instruction(ctx, ins); in emit_atomic()
1342 midgard_instruction ins = m_ld_vary_32(dest, PACK_LDST_ATTRIB_OFS(offset)); in emit_varying_read() local
1343 ins.mask = mask_of(nr_comp); in emit_varying_read()
1344 ins.dest_type = type; in emit_varying_read()
1348 ins.mask = mask_of(ALIGN_POT(nr_comp, 2)); in emit_varying_read()
1351 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i) in emit_varying_read()
1352 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W); in emit_varying_read()
1360 midgard_pack_varying_params(&ins.load_store, p); in emit_varying_read()
1363 ins.src[2] = nir_src_index(ctx, indirect_offset); in emit_varying_read()
1364 ins.src_types[2] = nir_type_uint32; in emit_varying_read()
1366 ins.load_store.index_reg = REGISTER_LDST_ZERO; in emit_varying_read()
1368 ins.load_store.arg_reg = REGISTER_LDST_ZERO; in emit_varying_read()
1369 ins.load_store.index_format = midgard_index_address_u32; in emit_varying_read()
1375 ins.op = midgard_op_ld_vary_32u; in emit_varying_read()
1378 ins.op = midgard_op_ld_vary_32i; in emit_varying_read()
1381 ins.op = midgard_op_ld_vary_32; in emit_varying_read()
1384 ins.op = midgard_op_ld_vary_16; in emit_varying_read()
1391 emit_mir_instruction(ctx, ins); in emit_varying_read()
1421 midgard_instruction ins; in emit_image_op() local
1427 ins = st_image(type, val, PACK_LDST_ATTRIB_OFS(address)); in emit_image_op()
1429 ins.src_types[0] = base_type | nir_src_bit_size(instr->src[3]); in emit_image_op()
1432 ins = m_lea_image(dest, PACK_LDST_ATTRIB_OFS(address)); in emit_image_op()
1433 ins.mask = mask_of(2); /* 64-bit memory address */ in emit_image_op()
1436 ins = ld_image(type, nir_dest_index(&instr->dest), PACK_LDST_ATTRIB_OFS(address)); in emit_image_op()
1437 ins.mask = mask_of(nir_intrinsic_dest_components(instr)); in emit_image_op()
1438 ins.dest_type = type; in emit_image_op()
1442 ins.src[1] = coord_reg; in emit_image_op()
1443 ins.src_types[1] = nir_type_uint16; in emit_image_op()
1445 ins.load_store.bitsize_toggle = true; in emit_image_op()
1450 ins.src[2] = nir_src_index(ctx, index); in emit_image_op()
1451 ins.src_types[2] = nir_type_uint32; in emit_image_op()
1453 ins.load_store.index_reg = REGISTER_LDST_ZERO; in emit_image_op()
1455 emit_mir_instruction(ctx, ins); in emit_image_op()
1457 return ins; in emit_image_op()
1466 midgard_instruction ins = m_ld_attr_32(dest, PACK_LDST_ATTRIB_OFS(offset)); in emit_attr_read() local
1467 ins.load_store.arg_reg = REGISTER_LDST_ZERO; in emit_attr_read()
1468 ins.load_store.index_reg = REGISTER_LDST_ZERO; in emit_attr_read()
1469 ins.mask = mask_of(nr_comp); in emit_attr_read()
1475 ins.op = midgard_op_ld_attr_32u; in emit_attr_read()
1478 ins.op = midgard_op_ld_attr_32i; in emit_attr_read()
1481 ins.op = midgard_op_ld_attr_32; in emit_attr_read()
1488 emit_mir_instruction(ctx, ins); in emit_attr_read()
1506 midgard_instruction *ins = in emit_sysval_read() local
1510 ins->mask = mask_of(nr_components); in emit_sysval_read()
1542 struct midgard_instruction ins = in emit_fragment_store() local
1547 ins.writeout = depth_only ? 0 : PAN_WRITEOUT_C; in emit_fragment_store()
1550 ins.src[0] = src; in emit_fragment_store()
1551 ins.src_types[0] = nir_type_uint32; in emit_fragment_store()
1554 ins.constants.u32[0] = 0xFF; in emit_fragment_store()
1556 ins.constants.u32[0] = ((rt - MIDGARD_COLOR_RT0) << 8) | sample_iter; in emit_fragment_store()
1559 ins.swizzle[0][i] = i; in emit_fragment_store()
1563 ins.src[2] = src_z; in emit_fragment_store()
1564 ins.src_types[2] = nir_type_uint32; in emit_fragment_store()
1565 ins.writeout |= PAN_WRITEOUT_Z; in emit_fragment_store()
1569 ins.src[3] = src_s; in emit_fragment_store()
1570 ins.src_types[3] = nir_type_uint32; in emit_fragment_store()
1571 ins.writeout |= PAN_WRITEOUT_S; in emit_fragment_store()
1575 br = emit_mir_instruction(ctx, ins); in emit_fragment_store()
1589 midgard_instruction ins = m_ldst_mov(reg, 0); in emit_compute_builtin() local
1590 ins.mask = mask_of(3); in emit_compute_builtin()
1591 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */ in emit_compute_builtin()
1592 ins.load_store.arg_reg = compute_builtin_arg(instr->intrinsic); in emit_compute_builtin()
1593 emit_mir_instruction(ctx, ins); in emit_compute_builtin()
1635 midgard_instruction ins = { in emit_control_barrier() local
1642 emit_mir_instruction(ctx, ins); in emit_control_barrier()
1893 midgard_instruction ins = v_mov(reg, out); in emit_intrinsic() local
1894 emit_mir_instruction(ctx, ins); in emit_intrinsic()
2183 midgard_instruction *ins) in set_tex_coord() argument
2198 ins->src_types[1] = nir_tex_instr_src_type(instr, coord_idx) | in set_tex_coord()
2209 ins->swizzle[1][c] = COMPONENT_X; in set_tex_coord()
2216 ins->swizzle[1][COMPONENT_Z] = --nr_comps; in set_tex_coord()
2226 ins->swizzle[1][COMPONENT_W] = --nr_comps; in set_tex_coord()
2232 assert(ins->op != midgard_tex_op_fetch); in set_tex_coord()
2234 ins->src[1] = make_compiler_temp_reg(ctx); in set_tex_coord()
2239 midgard_instruction ld = m_ld_cubemap_coords(ins->src[1], 0); in set_tex_coord()
2241 ld.src_types[1] = ins->src_types[1]; in set_tex_coord()
2258 ins->swizzle[1][c] = c; in set_tex_coord()
2269 if (ins->src[1] == ~0) in set_tex_coord()
2270 ins->src[1] = make_compiler_temp_reg(ctx); in set_tex_coord()
2272 midgard_instruction mov = v_mov(sample_or_ref, ins->src[1]); in set_tex_coord()
2279 ins->swizzle[1][COMPONENT_Z] = COMPONENT_Z; in set_tex_coord()
2287 if (ins->op == midgard_tex_op_fetch && in set_tex_coord()
2289 if (ins->src[1] == ~0) in set_tex_coord()
2290 ins->src[1] = make_compiler_temp_reg(ctx); in set_tex_coord()
2294 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), ins->src[1]); in set_tex_coord()
2300 ins->swizzle[1][c] = c; in set_tex_coord()
2304 if (ins->src[1] == ~0) { in set_tex_coord()
2306 ins->src[1] = coords; in set_tex_coord()
2309 midgard_instruction mov = v_mov(coords, ins->src[1]); in set_tex_coord()
2313 mov.swizzle[1][c] = ins->swizzle[1][c]; in set_tex_coord()
2314 ins->swizzle[1][c] = c; in set_tex_coord()
2345 midgard_instruction ins = { in emit_texop_native() local
2364 ins.swizzle[0][i] = COMPONENT_X; in emit_texop_native()
2373 set_tex_coord(ctx, instr, &ins); in emit_texop_native()
2381 … if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture)) in emit_texop_native()
2384 ins.texture.lod_register = true; in emit_texop_native()
2385 ins.src[2] = index; in emit_texop_native()
2386 ins.src_types[2] = T; in emit_texop_native()
2389 ins.swizzle[2][c] = COMPONENT_X; in emit_texop_native()
2397 ins.texture.offset_register = true; in emit_texop_native()
2398 ins.src[3] = index; in emit_texop_native()
2399 ins.src_types[3] = T; in emit_texop_native()
2402 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c; in emit_texop_native()
2420 emit_mir_instruction(ctx, ins); in emit_texop_native()
2540 … midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch); in inline_alu_constants() local
2541 attach_constants(ctx, &ins, entry, alu->src[1] + 1); in inline_alu_constants()
2547 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins); in inline_alu_constants()
2554 max_bitsize_for_alu(midgard_instruction *ins) in max_bitsize_for_alu() argument
2558 if (ins->src[i] == ~0) continue; in max_bitsize_for_alu()
2559 unsigned src_bitsize = nir_alu_type_get_type_size(ins->src_types[i]); in max_bitsize_for_alu()
2562 unsigned dst_bitsize = nir_alu_type_get_type_size(ins->dest_type); in max_bitsize_for_alu()
2573 switch (ins->op) { in max_bitsize_for_alu()
2590 if (midgard_is_integer_out_op(ins->op) && ins->outmod == midgard_outmod_keephi) { in max_bitsize_for_alu()
2623 mir_foreach_instr_in_block(block, ins) { in embedded_to_inline_constant()
2624 if (!ins->has_constants) continue; in embedded_to_inline_constant()
2625 if (ins->has_inline_constant) continue; in embedded_to_inline_constant()
2627 unsigned max_bitsize = max_bitsize_for_alu(ins); in embedded_to_inline_constant()
2640 int op = ins->op; in embedded_to_inline_constant()
2642 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) && in embedded_to_inline_constant()
2644 mir_flip(ins); in embedded_to_inline_constant()
2647 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) { in embedded_to_inline_constant()
2649 assert(ins->mask); in embedded_to_inline_constant()
2650 unsigned first_comp = ffs(ins->mask) - 1; in embedded_to_inline_constant()
2651 unsigned component = ins->swizzle[1][first_comp]; in embedded_to_inline_constant()
2657 scaled_constant = ins->constants.u16[component]; in embedded_to_inline_constant()
2659 scaled_constant = ins->constants.u32[component]; in embedded_to_inline_constant()
2662 if (scaled_constant != ins->constants.u32[component]) in embedded_to_inline_constant()
2665 float original = ins->constants.f32[component]; in embedded_to_inline_constant()
2682 if (ins->src_abs[1] || ins->src_neg[1]) in embedded_to_inline_constant()
2688 const midgard_constants *cons = &ins->constants; in embedded_to_inline_constant()
2692 unsigned mask = effective_writemask(ins->op, ins->mask); in embedded_to_inline_constant()
2700 cons->u16[ins->swizzle[1][c]] : in embedded_to_inline_constant()
2701 cons->u32[ins->swizzle[1][c]]; in embedded_to_inline_constant()
2713 ins->has_constants = false; in embedded_to_inline_constant()
2714 ins->src[1] = ~0; in embedded_to_inline_constant()
2715 ins->has_inline_constant = true; in embedded_to_inline_constant()
2716 ins->inline_constant = scaled_constant; in embedded_to_inline_constant()
2729 mir_foreach_instr_in_block_safe(block, ins) { in midgard_cull_dead_branch()
2730 if (!midgard_is_branch_unit(ins->unit)) continue; in midgard_cull_dead_branch()
2733 mir_remove_instruction(ins); in midgard_cull_dead_branch()
2749 mir_foreach_instr_in_block(block, ins) { in midgard_legalize_invert()
2750 if (ins->type != TAG_ALU_4) continue; in midgard_legalize_invert()
2752 if (ins->op != midgard_alu_op_iand && in midgard_legalize_invert()
2753 ins->op != midgard_alu_op_ior) continue; in midgard_legalize_invert()
2755 if (ins->src_invert[1] || !ins->src_invert[0]) continue; in midgard_legalize_invert()
2757 if (ins->has_inline_constant) { in midgard_legalize_invert()
2760 ins->inline_constant = ~ins->inline_constant; in midgard_legalize_invert()
2761 ins->src_invert[1] = true; in midgard_legalize_invert()
2766 mir_flip(ins); in midgard_legalize_invert()
2776 struct midgard_instruction ins = v_branch(false, false); in emit_fragment_epilogue() local
2777 ins.writeout = br->writeout; in emit_fragment_epilogue()
2778 ins.branch.target_block = ctx->block_count - 1; in emit_fragment_epilogue()
2779 ins.constants.u32[0] = br->constants.u32[0]; in emit_fragment_epilogue()
2780 memcpy(&ins.src_types, &br->src_types, sizeof(ins.src_types)); in emit_fragment_epilogue()
2781 emit_mir_instruction(ctx, ins); in emit_fragment_epilogue()
2785 return ins.branch.target_block; in emit_fragment_epilogue()
2911 mir_foreach_instr_in_block(((midgard_block *) _block), ins) { in emit_loop()
2912 if (ins->type != TAG_ALU_4) continue; in emit_loop()
2913 if (!ins->compact_branch) continue; in emit_loop()
2916 if (ins->branch.target_type != TARGET_BREAK) continue; in emit_loop()
2919 if (ins->branch.target_break != loop_idx) continue; in emit_loop()
2924 ins->branch.target_type = TARGET_GOTO; in emit_loop()
2925 ins->branch.target_block = break_block_idx; in emit_loop()