Lines Matching refs:ins
188 mir_foreach_instr_global(ctx, ins) { in mir_lower_special_reads()
189 switch (ins->type) { in mir_lower_special_reads()
191 mark_node_class(aluw, ins->dest); in mir_lower_special_reads()
192 mark_node_class(alur, ins->src[0]); in mir_lower_special_reads()
193 mark_node_class(alur, ins->src[1]); in mir_lower_special_reads()
194 mark_node_class(alur, ins->src[2]); in mir_lower_special_reads()
196 if (ins->compact_branch && ins->writeout) in mir_lower_special_reads()
197 mark_node_class(brar, ins->src[0]); in mir_lower_special_reads()
202 mark_node_class(aluw, ins->dest); in mir_lower_special_reads()
203 mark_node_class(ldst, ins->src[0]); in mir_lower_special_reads()
204 mark_node_class(ldst, ins->src[1]); in mir_lower_special_reads()
205 mark_node_class(ldst, ins->src[2]); in mir_lower_special_reads()
206 mark_node_class(ldst, ins->src[3]); in mir_lower_special_reads()
210 mark_node_class(texr, ins->src[0]); in mir_lower_special_reads()
211 mark_node_class(texr, ins->src[1]); in mir_lower_special_reads()
212 mark_node_class(texr, ins->src[2]); in mir_lower_special_reads()
213 mark_node_class(texw, ins->dest); in mir_lower_special_reads()
332 mir_foreach_instr_in_block_rev(block, ins) { in mir_compute_interference()
333 if (ins->writeout) in mir_compute_interference()
334 r1w = ins->dest; in mir_compute_interference()
341 mir_foreach_instr_global(ctx, ins) { in mir_compute_interference()
342 if (ins->dest < ctx->temp_count) in mir_compute_interference()
343 … lcra_add_node_interference(l, ins->dest, mir_bytemask(ins), r1w, 0xF); in mir_compute_interference()
355 mir_foreach_instr_in_block_rev(blk, ins) { in mir_compute_interference()
359 unsigned dest = ins->dest; in mir_compute_interference()
364 unsigned mask = mir_bytemask(ins); in mir_compute_interference()
372 if (ins->compact_branch && ins->writeout) { in mir_compute_interference()
386 mir_liveness_ins_update(live, ins, ctx->temp_count); in mir_compute_interference()
394 mir_is_64(midgard_instruction *ins) in mir_is_64() argument
396 if (nir_alu_type_get_type_size(ins->dest_type) == 64) in mir_is_64()
399 mir_foreach_src(ins, v) { in mir_is_64()
400 if (nir_alu_type_get_type_size(ins->src_types[v]) == 64) in mir_is_64()
457 mir_foreach_instr_global(ctx, ins) { in allocate_registers()
464 if (ins->type == TAG_ALU_4 && mir_is_64(ins)) { in allocate_registers()
465 mir_foreach_src(ins, v) { in allocate_registers()
466 unsigned s = ins->src[v]; in allocate_registers()
473 if (ins->type == TAG_LOAD_STORE_4 && OP_HAS_ADDRESS(ins->op)) { in allocate_registers()
474 mir_foreach_src(ins, v) { in allocate_registers()
475 unsigned s = ins->src[v]; in allocate_registers()
476 unsigned size = nir_alu_type_get_type_size(ins->src_types[v]); in allocate_registers()
483 if (ins->dest >= SSA_FIXED_MINIMUM) continue; in allocate_registers()
485 unsigned size = nir_alu_type_get_type_size(ins->dest_type); in allocate_registers()
487 if (ins->is_pack) in allocate_registers()
491 int comps1 = util_logbase2(ins->mask); in allocate_registers()
498 int dest = ins->dest; in allocate_registers()
511 mir_foreach_src(ins, s) { in allocate_registers()
512 unsigned src_size = nir_alu_type_get_type_size(ins->src_types[s]); in allocate_registers()
513 if (src_size == 16 && ins->src[s] < SSA_FIXED_MINIMUM) in allocate_registers()
514 min_bound[ins->src[s]] = MAX2(min_bound[ins->src[s]], 8); in allocate_registers()
521 if (ins->type == TAG_ALU_4 && OP_IS_CSEL_V(ins->op)) { in allocate_registers()
530 if (ins->type == TAG_LOAD_STORE_4) in allocate_registers()
551 mir_foreach_instr_global(ctx, ins) { in allocate_registers()
554 if (ins->type == TAG_LOAD_STORE_4) { in allocate_registers()
555 set_class(l->class, ins->src[0], REG_CLASS_LDST); in allocate_registers()
556 set_class(l->class, ins->src[1], REG_CLASS_LDST); in allocate_registers()
557 set_class(l->class, ins->src[2], REG_CLASS_LDST); in allocate_registers()
558 set_class(l->class, ins->src[3], REG_CLASS_LDST); in allocate_registers()
560 if (OP_IS_VEC4_ONLY(ins->op)) { in allocate_registers()
561 lcra_restrict_range(l, ins->dest, 16); in allocate_registers()
562 lcra_restrict_range(l, ins->src[0], 16); in allocate_registers()
563 lcra_restrict_range(l, ins->src[1], 16); in allocate_registers()
564 lcra_restrict_range(l, ins->src[2], 16); in allocate_registers()
565 lcra_restrict_range(l, ins->src[3], 16); in allocate_registers()
567 } else if (ins->type == TAG_TEXTURE_4) { in allocate_registers()
568 set_class(l->class, ins->dest, REG_CLASS_TEXW); in allocate_registers()
569 set_class(l->class, ins->src[0], REG_CLASS_TEXR); in allocate_registers()
570 set_class(l->class, ins->src[1], REG_CLASS_TEXR); in allocate_registers()
571 set_class(l->class, ins->src[2], REG_CLASS_TEXR); in allocate_registers()
572 set_class(l->class, ins->src[3], REG_CLASS_TEXR); in allocate_registers()
577 mir_foreach_instr_global(ctx, ins) { in allocate_registers()
578 assert(check_write_class(l->class, ins->type, ins->dest)); in allocate_registers()
579 assert(check_read_class(l->class, ins->type, ins->src[0])); in allocate_registers()
580 assert(check_read_class(l->class, ins->type, ins->src[1])); in allocate_registers()
581 assert(check_read_class(l->class, ins->type, ins->src[2])); in allocate_registers()
582 assert(check_read_class(l->class, ins->type, ins->src[3])); in allocate_registers()
587 mir_foreach_instr_global(ctx, ins) { in allocate_registers()
588 if (!(ins->compact_branch && ins->writeout)) continue; in allocate_registers()
590 if (ins->src[0] < ctx->temp_count) in allocate_registers()
591 l->solutions[ins->src[0]] = 0; in allocate_registers()
593 if (ins->src[2] < ctx->temp_count) in allocate_registers()
594 l->solutions[ins->src[2]] = (16 * 1) + COMPONENT_X * 4; in allocate_registers()
596 if (ins->src[3] < ctx->temp_count) in allocate_registers()
597 l->solutions[ins->src[3]] = (16 * 1) + COMPONENT_Y * 4; in allocate_registers()
599 if (ins->src[1] < ctx->temp_count) in allocate_registers()
600 l->solutions[ins->src[1]] = (16 * 1) + COMPONENT_Z * 4; in allocate_registers()
602 if (ins->dest < ctx->temp_count) in allocate_registers()
603 l->solutions[ins->dest] = (16 * 1) + COMPONENT_W * 4; in allocate_registers()
637 midgard_instruction *ins = v->instructions[i]; in allocate_registers() local
639 if (ins->dest >= ctx->temp_count) in allocate_registers()
642 bool used_as_r1 = (br->dest == ins->dest); in allocate_registers()
645 used_as_r1 |= (s > 0) && (br->src[s] == ins->dest); in allocate_registers()
648 … lcra_add_node_interference(l, ins->dest, mir_bytemask(ins), node_r1, 0xFFFF); in allocate_registers()
687 midgard_instruction *ins) in install_registers_instr() argument
693 util_logbase2(nir_alu_type_get_type_size(ins->src_types[i]) / 8); in install_registers_instr()
697 util_logbase2(nir_alu_type_get_type_size(ins->dest_type) / 8); in install_registers_instr()
699 switch (ins->type) { in install_registers_instr()
704 if (ins->compact_branch) in install_registers_instr()
707 struct phys_reg src1 = index_to_reg(ctx, l, ins->src[0], src_shift[0]); in install_registers_instr()
708 struct phys_reg src2 = index_to_reg(ctx, l, ins->src[1], src_shift[1]); in install_registers_instr()
709 struct phys_reg dest = index_to_reg(ctx, l, ins->dest, dest_shift); in install_registers_instr()
711 mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset); in install_registers_instr()
714 GET_CHANNEL_COUNT(alu_opcode_props[ins->op].props) ? 0 : in install_registers_instr()
717 offset_swizzle(ins->swizzle[0], src1.offset, src1.shift, dest.shift, dest_offset); in install_registers_instr()
718 if (!ins->has_inline_constant) in install_registers_instr()
719 … offset_swizzle(ins->swizzle[1], src2.offset, src2.shift, dest.shift, dest_offset); in install_registers_instr()
720 if (ins->src[0] != ~0) in install_registers_instr()
721 ins->src[0] = SSA_FIXED_REGISTER(src1.reg); in install_registers_instr()
722 if (ins->src[1] != ~0) in install_registers_instr()
723 ins->src[1] = SSA_FIXED_REGISTER(src2.reg); in install_registers_instr()
724 if (ins->dest != ~0) in install_registers_instr()
725 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr()
734 bool encodes_src = OP_IS_STORE(ins->op); in install_registers_instr()
737 struct phys_reg src = index_to_reg(ctx, l, ins->src[0], src_shift[0]); in install_registers_instr()
740 ins->src[0] = SSA_FIXED_REGISTER(src.reg); in install_registers_instr()
741 offset_swizzle(ins->swizzle[0], src.offset, src.shift, 0, 0); in install_registers_instr()
743 struct phys_reg dst = index_to_reg(ctx, l, ins->dest, dest_shift); in install_registers_instr()
745 ins->dest = SSA_FIXED_REGISTER(dst.reg); in install_registers_instr()
746 offset_swizzle(ins->swizzle[0], 0, 2, 2, dst.offset); in install_registers_instr()
747 mir_set_bytemask(ins, mir_bytemask(ins) << dst.offset); in install_registers_instr()
753 unsigned src_index = ins->src[i]; in install_registers_instr()
758 ins->src[i] = SSA_FIXED_REGISTER(src.reg); in install_registers_instr()
759 ins->swizzle[i][0] += component; in install_registers_instr()
767 if (ins->op == midgard_tex_op_barrier) in install_registers_instr()
771 struct phys_reg dest = index_to_reg(ctx, l, ins->dest, dest_shift); in install_registers_instr()
772 struct phys_reg coord = index_to_reg(ctx, l, ins->src[1], src_shift[1]); in install_registers_instr()
773 struct phys_reg lod = index_to_reg(ctx, l, ins->src[2], src_shift[2]); in install_registers_instr()
774 struct phys_reg offset = index_to_reg(ctx, l, ins->src[3], src_shift[3]); in install_registers_instr()
777 if (ins->src[1] != ~0) in install_registers_instr()
778 ins->src[1] = SSA_FIXED_REGISTER(coord.reg); in install_registers_instr()
779 offset_swizzle(ins->swizzle[1], coord.offset, coord.shift, dest.shift, 0); in install_registers_instr()
782 if (ins->dest != ~0) in install_registers_instr()
783 ins->dest = SSA_FIXED_REGISTER(dest.reg); in install_registers_instr()
784 offset_swizzle(ins->swizzle[0], 0, 2, dest.shift, in install_registers_instr()
787 mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset); in install_registers_instr()
790 if (ins->src[2] != ~0) { in install_registers_instr()
792 ins->src[2] = SSA_FIXED_REGISTER(lod.reg); in install_registers_instr()
793 ins->swizzle[2][0] = lod.offset / 4; in install_registers_instr()
797 if (ins->src[3] != ~0) { in install_registers_instr()
798 ins->src[3] = SSA_FIXED_REGISTER(offset.reg); in install_registers_instr()
799 ins->swizzle[3][0] = offset.offset / 4; in install_registers_instr()
813 mir_foreach_instr_global(ctx, ins) in install_registers()
814 install_registers_instr(ctx, l, ins); in install_registers()
827 mir_foreach_instr_global(ctx, ins) { in mir_choose_spill_node()
828 if (ins->no_spill & (1 << l->spill_class)) { in mir_choose_spill_node()
829 lcra_set_node_spill_cost(l, ins->dest, -1); in mir_choose_spill_node()
832 mir_foreach_src(ins, s) in mir_choose_spill_node()
833 lcra_set_node_spill_cost(l, ins->src[s], -1); in mir_choose_spill_node()
872 mir_foreach_instr_global_safe(ctx, ins) { in mir_spill_register()
873 read_bytemask |= mir_bytemask_of_read_components(ins, spill_node); in mir_spill_register()
874 if (ins->dest == spill_node) in mir_spill_register()
888 mir_foreach_instr_in_block_safe(block, ins) { in mir_spill_register()
889 if (ins->dest != spill_node) continue; in mir_spill_register()
900 st.mask = ins->mask; in mir_spill_register()
901 st.dest_type = st.src_types[1] = ins->dest_type; in mir_spill_register()
906 mir_insert_instruction_after_scheduled(ctx, block, ins, st); in mir_spill_register()
910 if (write_count > 1 && mir_bytemask(ins) != 0xF) { in mir_spill_register()
913 … mir_insert_instruction_before_scheduled(ctx, block, ins, read); in mir_spill_register()
916 ins->dest = dest; in mir_spill_register()
917 ins->no_spill |= (1 << spill_class); in mir_spill_register()
923 midgard_instruction *it = ins; in mir_spill_register()
925 && (it->bundle_id == ins->bundle_id)) { in mir_spill_register()
941 v_load_store_scratch(dest, spill_slot, true, ins->mask); in mir_spill_register()
942 mir_insert_instruction_after_scheduled(ctx, block, ins, st); in mir_spill_register()
945 midgard_instruction mv = v_mov(ins->dest, dest); in mir_spill_register()
948 mir_insert_instruction_after_scheduled(ctx, block, ins, mv); in mir_spill_register()
969 mir_foreach_instr_in_block(block, ins) { in mir_spill_register()
972 if (ins->hint) continue; in mir_spill_register()
975 if (!mir_has_arg(ins, spill_node)) continue; in mir_spill_register()
982 midgard_instruction *before = ins; in mir_spill_register()
1008 mir_rewrite_index_src_single(ins, spill_node, index); in mir_spill_register()
1017 mir_foreach_instr_global(ctx, ins) { in mir_spill_register()
1018 ins->hint = false; in mir_spill_register()
1034 mir_foreach_instr_in_block(block, ins) { in mir_demote_uniforms()
1035 mir_foreach_src(ins, i) { in mir_demote_uniforms()
1036 if (ins->src[i] < min_demote || ins->src[i] >= max_demote) in mir_demote_uniforms()
1039 midgard_instruction *before = ins; in mir_demote_uniforms()
1042 unsigned idx = (23 - SSA_REG_FROM_FIXED(ins->src[i])) * 4; in mir_demote_uniforms()
1051 .dest_type = ins->src_types[i], in mir_demote_uniforms()
1066 mir_rewrite_index_src_single(ins, ins->src[i], temp); in mir_demote_uniforms()