Lines Matching refs:availability

26 =item bit #19 denoting availability of CLFLUSH instruction;
32 =item bit #24, FXSR bit, denoting availability of XMM registers;
43 =item bit #33 denoting availability of PCLMULQDQ instruction;
49 =item bit #54 denoting availability of MOVBE instruction;
56 =item bit #59, OSXSAVE bit, denoting availability of YMM registers;
60 =item bit #62 denoting availability of RDRAND instruction;
91 =item bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;
93 =item bit #64+5 denoting availability of AVX2 instructions;
95 =item bit #64+8 denoting availability of BMI2 instructions, e.g. MULX
98 =item bit #64+16 denoting availability of AVX512F extension;
100 =item bit #64+18 denoting availability of RDSEED instruction;
102 =item bit #64+19 denoting availability of ADCX and ADOX instructions;
104 =item bit #64+21 denoting availability of VPMADD52[LH]UQ instructions,
107 =item bit #64+29 denoting availability of SHA extension;
109 =item bit #64+30 denoting availability of AVX512BW extension;
111 =item bit #64+31 denoting availability of AVX512VL extension;
113 =item bit #64+41 denoting availability of VAES extension;
115 =item bit #64+42 denoting availability of VPCLMULQDQ extension;