Lines Matching refs:width

869 +			bus-width = <4>;
885 +			bus-width = <4>;
905 +			bus-width = <4>;
15348 +static u32 get_width(enum dma_slave_buswidth width)
15350 +	switch (width) {
15360 +		hiedmacv310_error("check here, width warning!\n");
15370 +	unsigned int config, width;
15378 +	width = get_width(addr_width);
15379 +	hiedmacv310_trace(HIEDMACV310_CONFIG_TRACE_LEVEL, "width = 0x%x\n", width);
15380 +	config |= width << HIEDMAC_CONFIG_SRC_WIDTH_SHIFT;
15381 +	config |= width << HIEDMAC_CONFIG_DST_WIDTH_SHIFT;
15580 +	unsigned short width = get_max_width(tsf_desc->ccfg);
15584 +		lli_len = (lli_len / width) * width; /* bus width align */
15699 +	/*  max burst width is 16 ,but reg value set 0xf */
16505 +    unsigned int width;
16635 +    cap->layer_cap[DRM_HAL_GFX_G0].max_w = 1920; /* 1920 max width */
16647 +    cap->layer_cap[DRM_HAL_GFX_G3].max_w = 256; /* 256 max width */
16873 +    hal_rect.w = fb->width;
17837 +    .hdisplay = 400, /* 400 width */
29554 +	if (of_property_read_u32(np, "bus-width", &bus_width) == 0) {
29557 +		pr_err("%s: \"bus-width\" property is missing, assuming 1 bit.\n",
35923 +	int "the width of Read/Write HIGH Hold Time (0 to 15)"
35930 +	int "the Read pulse width (0 to 15)"
35937 +	int "the Write pulse width (0 to 15)"
40496 +	bool "higmac ddr width 64 bit"
40500 +	  This define the higmac supports DDR width 64 bit.
40502 +	  But in old version, the higmac only supports DDR width 32 bit.
49863 +	 set to 128 byte, and the problem of VDP low band width also be avoided.
57063  	video->width = 320;
59319 +#define I2C_M_16BIT_REG		0x0002	/* indicate reg bit-width is 16bit */
59320 +#define I2C_M_16BIT_DATA	0x0008	/* indicate data bit-width is 16bit */