Destination register is opposite precision as source, ie. if {FULL} is true then destination is half precision, and visa versa. Full precision source registers 010 !!(src->flags & IR3_INSTR_SAT) ((src->dsts[0]->num >> 2) == 62) ? 0 : !!((src->srcs[0]->flags ^ src->dsts[0]->flags) & IR3_REG_HALF) !!(src->dsts[0]->flags & IR3_REG_EI) !(src->srcs[0]->flags & IR3_REG_HALF) extract_SRC1_R(src) extract_SRC2_R(src) {SY}{SS}{JP}{SAT}(nop{NOP}) {UL}{NAME} {EI}{DST_HALF}{DST}, {SRC1} {SY}{SS}{JP}{SAT}{REPEAT}{UL}{NAME} {EI}{DST_HALF}{DST}, {SRC1} xxxxxxxxxxxxxxxx xxx {SY}{SS}{JP}{SAT}(nop{NOP}) {UL}{NAME} {EI}{DST_HALF}{DST}, {SRC1}, {SRC2} {SY}{SS}{JP}{SAT}{REPEAT}{UL}{NAME} {EI}{DST_HALF}{DST}, {SRC1}, {SRC2} xxx {SY}{SS}{JP}{SAT}(nop{NOP}) {UL}{NAME}.{COND} {EI}{DST_HALF}{DST}, {SRC1}, {SRC2} {SY}{SS}{JP}{SAT}{REPEAT}{UL}{NAME}.{COND} {EI}{DST_HALF}{DST}, {SRC1}, {SRC2} src->cat2.condition 000000 000001 000010 000011 000100 000101 000110 000111 001001 001010 001011 001100 001101 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011100 011101 011110 011111 100001 100010 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111